* [PATCH 0/2] riscv: smp: Two minor comment updates
@ 2026-02-04 3:20 Vivian Wang
2026-02-04 3:20 ` [PATCH 1/2] riscv: smp: Remove outdated comment about disabling preemption Vivian Wang
` (2 more replies)
0 siblings, 3 replies; 4+ messages in thread
From: Vivian Wang @ 2026-02-04 3:20 UTC (permalink / raw)
To: Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti,
Ingo Molnar, Valentin Schneider, Peter Zijlstra, Samuel Holland
Cc: linux-riscv, linux-kernel, Palmer Dabbelt, Vivian Wang
I happened to be digging around these bits and saw these comments that
confused me for a sec. So, might as well update them for the sake of
future readers.
---
Vivian Wang (2):
riscv: smp: Remove outdated comment about disabling preemption
riscv: smp: Clarify comment "cache" -> "instruction cache"
arch/riscv/kernel/smpboot.c | 8 ++------
1 file changed, 2 insertions(+), 6 deletions(-)
---
base-commit: 8f0b4cce4481fb22653697cced8d0d04027cb1e8
change-id: 20260204-riscv-smp-comment-update-2026-01-7e75e3a2261a
Best regards,
--
Vivian "dramforever" Wang
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^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH 1/2] riscv: smp: Remove outdated comment about disabling preemption
2026-02-04 3:20 [PATCH 0/2] riscv: smp: Two minor comment updates Vivian Wang
@ 2026-02-04 3:20 ` Vivian Wang
2026-02-04 3:20 ` [PATCH 2/2] riscv: smp: Clarify comment "cache" -> "instruction cache" Vivian Wang
2026-02-13 0:24 ` [PATCH 0/2] riscv: smp: Two minor comment updates Paul Walmsley
2 siblings, 0 replies; 4+ messages in thread
From: Vivian Wang @ 2026-02-04 3:20 UTC (permalink / raw)
To: Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti,
Ingo Molnar, Valentin Schneider, Peter Zijlstra, Samuel Holland
Cc: linux-riscv, linux-kernel, Palmer Dabbelt, Vivian Wang
Commit f1a0a376ca0c ("sched/core: Initialize the idle task with
preemption disabled") removed a call to preempt_disable(), but not the
associated comment. Remove the outdated comment.
Fixes: f1a0a376ca0c ("sched/core: Initialize the idle task with preemption disabled")
Signed-off-by: Vivian Wang <wangruikang@iscas.ac.cn>
---
| 4 ----
1 file changed, 4 deletions(-)
--git a/arch/riscv/kernel/smpboot.c b/arch/riscv/kernel/smpboot.c
index d85916a3660c..0e6fe20c69a2 100644
--- a/arch/riscv/kernel/smpboot.c
+++ b/arch/riscv/kernel/smpboot.c
@@ -259,10 +259,6 @@ asmlinkage __visible void smp_callin(void)
#ifndef CONFIG_HOTPLUG_PARALLEL
complete(&cpu_running);
#endif
- /*
- * Disable preemption before enabling interrupts, so we don't try to
- * schedule a CPU that hasn't actually started yet.
- */
local_irq_enable();
cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
}
--
2.52.0
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^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH 2/2] riscv: smp: Clarify comment "cache" -> "instruction cache"
2026-02-04 3:20 [PATCH 0/2] riscv: smp: Two minor comment updates Vivian Wang
2026-02-04 3:20 ` [PATCH 1/2] riscv: smp: Remove outdated comment about disabling preemption Vivian Wang
@ 2026-02-04 3:20 ` Vivian Wang
2026-02-13 0:24 ` [PATCH 0/2] riscv: smp: Two minor comment updates Paul Walmsley
2 siblings, 0 replies; 4+ messages in thread
From: Vivian Wang @ 2026-02-04 3:20 UTC (permalink / raw)
To: Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti,
Ingo Molnar, Valentin Schneider, Peter Zijlstra, Samuel Holland
Cc: linux-riscv, linux-kernel, Palmer Dabbelt, Vivian Wang
local_flush_icache_all() only flushes and synchronizes the *instruction*
cache, not the data cache. Since RISC-V does have a cbo.flush
instruction for data cache flush, clarify the comment to avoid
confusion.
Fixes: 58661a30f1bc ("riscv: Flush the instruction cache during SMP bringup")
Signed-off-by: Vivian Wang <wangruikang@iscas.ac.cn>
---
| 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
--git a/arch/riscv/kernel/smpboot.c b/arch/riscv/kernel/smpboot.c
index 0e6fe20c69a2..8b628580fe11 100644
--- a/arch/riscv/kernel/smpboot.c
+++ b/arch/riscv/kernel/smpboot.c
@@ -251,8 +251,8 @@ asmlinkage __visible void smp_callin(void)
set_cpu_online(curr_cpuid, true);
/*
- * Remote cache and TLB flushes are ignored while the CPU is offline,
- * so flush them both right now just in case.
+ * Remote instruction cache and TLB flushes are ignored while the CPU
+ * is offline, so flush them both right now just in case.
*/
local_flush_icache_all();
local_flush_tlb_all();
--
2.52.0
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^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH 0/2] riscv: smp: Two minor comment updates
2026-02-04 3:20 [PATCH 0/2] riscv: smp: Two minor comment updates Vivian Wang
2026-02-04 3:20 ` [PATCH 1/2] riscv: smp: Remove outdated comment about disabling preemption Vivian Wang
2026-02-04 3:20 ` [PATCH 2/2] riscv: smp: Clarify comment "cache" -> "instruction cache" Vivian Wang
@ 2026-02-13 0:24 ` Paul Walmsley
2 siblings, 0 replies; 4+ messages in thread
From: Paul Walmsley @ 2026-02-13 0:24 UTC (permalink / raw)
To: Vivian Wang
Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti,
Ingo Molnar, Valentin Schneider, Peter Zijlstra, Samuel Holland,
linux-riscv, linux-kernel, Palmer Dabbelt
On Wed, 4 Feb 2026, Vivian Wang wrote:
> I happened to be digging around these bits and saw these comments that
> confused me for a sec. So, might as well update them for the sake of
> future readers.
Thanks, queued for v7.0-rc.
- Paul
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2026-02-04 3:20 [PATCH 0/2] riscv: smp: Two minor comment updates Vivian Wang
2026-02-04 3:20 ` [PATCH 1/2] riscv: smp: Remove outdated comment about disabling preemption Vivian Wang
2026-02-04 3:20 ` [PATCH 2/2] riscv: smp: Clarify comment "cache" -> "instruction cache" Vivian Wang
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