From: Minda Chen <minda.chen@starfivetech.com>
To: Conor Dooley <conor.dooley@microchip.com>
Cc: Conor Dooley <conor@kernel.org>,
Jisheng Zhang <jszhang@kernel.org>,
Samuel Holland <samuel@sholland.org>, Dao Lu <daolu@rivosinc.com>,
"Heiko Stuebner" <heiko@sntech.de>,
Paul Walmsley <paul.walmsley@sifive.com>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>, <linux-kernel@vger.kernel.org>,
<linux-riscv@lists.infradead.org>,
Mason Huo <mason.huo@starfivetech.com>
Subject: Re: [PATCH v1] riscv: Using TOOLCHAIN_HAS_ZIHINTPAUSE marco replace zihintpause
Date: Wed, 2 Aug 2023 15:32:15 +0800 [thread overview]
Message-ID: <d64874cb-8628-a6d2-d2f4-8af4d0ebf8b2@starfivetech.com> (raw)
In-Reply-To: <20230802-sharpness-spoon-f9b8804fb66f@wendy>
On 2023/8/2 14:54, Conor Dooley wrote:
> Hey Minda,
>
> On Wed, Aug 02, 2023 at 02:42:15PM +0800, Minda Chen wrote:
>> Actually it is a part of Conor's
>> commit aae538cd03bc ("riscv: fix detection of toolchain
>> Zihintpause support").
>> It is looks like a merge issue.
>
> Yup, spot on.
>
>> Samuel's
>> commit 0b1d60d6dd9e ("riscv: Fix build with
>> CONFIG_CC_OPTIMIZE_FOR_SIZE=y") do not base on Conor's commit and
>> revert to __riscv_zihintpause. So this patch can fix it.
>>
>> Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
>
> Did you actually manage to trigger this, or was this by inspection?
> clang-15 + binutils 2.35 was, IIRC, how we spotted this because that's
> what the clang-built-linux CI uses to test the LTS kernels from before
> LLVM's IAS was supported for RISC-V. Seemingly all that needs to be
> satisfied there is that zihintpause doesn't appear in -march so this has
> gone unnoticed.
>
> Fixes: 3c349eacc559 ("Merge patch "riscv: Fix build with CONFIG_CC_OPTIMIZE_FOR_SIZE=y"")
> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
>
> Thanks,
> Conor.
>
Thanks, Conor. I found this just by inspection. I found a issue that vdso.so call cpu_relax
cause application core dump in kernel 6.1.31. I need Samuel'patch to fix this. And I search the log
of processor.h found this issue.
>> ---
>> arch/riscv/include/asm/vdso/processor.h | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/arch/riscv/include/asm/vdso/processor.h b/arch/riscv/include/asm/vdso/processor.h
>> index 14f5d27783b8..96b65a5396df 100644
>> --- a/arch/riscv/include/asm/vdso/processor.h
>> +++ b/arch/riscv/include/asm/vdso/processor.h
>> @@ -14,7 +14,7 @@ static inline void cpu_relax(void)
>> __asm__ __volatile__ ("div %0, %0, zero" : "=r" (dummy));
>> #endif
>>
>> -#ifdef __riscv_zihintpause
>> +#ifdef CONFIG_TOOLCHAIN_HAS_ZIHINTPAUSE
>> /*
>> * Reduce instruction retirement.
>> * This assumes the PC changes.
>> --
>> 2.17.1
>>
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next prev parent reply other threads:[~2023-08-02 7:32 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-08-02 6:42 [PATCH v1] riscv: Using TOOLCHAIN_HAS_ZIHINTPAUSE marco replace zihintpause Minda Chen
2023-08-02 6:54 ` Conor Dooley
2023-08-02 7:32 ` Minda Chen [this message]
2023-08-02 7:48 ` Conor Dooley
2023-08-02 8:17 ` Minda Chen
2023-08-02 8:33 ` Greg KH
2023-08-02 8:52 ` Conor Dooley
2023-08-02 9:42 ` Greg KH
2023-08-02 9:50 ` Conor Dooley
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