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Fri, 15 Mar 2024 16:34:00 -0700 (PDT) Received: from [100.64.0.1] ([136.226.86.189]) by smtp.gmail.com with ESMTPSA id bf16-20020a056e02309000b0036662e12737sm1013540ilb.44.2024.03.15.16.33.57 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 15 Mar 2024 16:33:59 -0700 (PDT) Message-ID: Date: Fri, 15 Mar 2024 18:33:57 -0500 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 3/4] cache: Add StarLink-500 cache management for StarFive JH8100 RISC-V core Content-Language: en-US To: Joshua Yeong References: <20240314061205.26143-1-joshua.yeong@starfivetech.com> <20240314061205.26143-4-joshua.yeong@starfivetech.com> From: Samuel Holland In-Reply-To: <20240314061205.26143-4-joshua.yeong@starfivetech.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240315_163401_586072_DF368FF4 X-CRM114-Status: GOOD ( 24.27 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: heiko@sntech.de, geert+renesas@glider.be, conor.dooley@microchip.com, guoren@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-riscv@lists.infradead.org, jeeheng.sia@starfivetech.com, ajones@ventanamicro.com, devicetree@vger.kernel.org, conor+dt@kernel.org, aou@eecs.berkeley.edu, alexghiti@rivosinc.com, leyfoon.tan@starfivetech.com, prabhakar.mahadev-lad.rj@bp.renesas.com, robh+dt@kernel.org, paul.walmsley@sifive.com, jszhang@kernel.org, linux-kernel@vger.kernel.org, conor@kernel.org, evan@rivosinc.com, palmer@dabbelt.com Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On 2024-03-14 1:12 AM, Joshua Yeong wrote: > Add software workaround for StarFive StarLink-500 > on JH8100 SoC for CMO extension instructions. > > Signed-off-by: Joshua Yeong > --- > drivers/cache/Kconfig | 9 ++ > drivers/cache/Makefile | 1 + > drivers/cache/starlink500_cache.c | 137 ++++++++++++++++++++++++++++++ > 3 files changed, 147 insertions(+) > create mode 100644 drivers/cache/starlink500_cache.c > > diff --git a/drivers/cache/Kconfig b/drivers/cache/Kconfig > index 9345ce4976d7..e215379f6a73 100644 > --- a/drivers/cache/Kconfig > +++ b/drivers/cache/Kconfig > @@ -14,4 +14,13 @@ config SIFIVE_CCACHE > help > Support for the composable cache controller on SiFive platforms. > > +config STARLINK_500_CACHE > + bool "StarLink-500 Cache controller" > + depends on RISCV_DMA_NONCOHERENT > + depends on ERRATA_STARFIVE > + select RISCV_NONSTANDARD_CACHE_OPS > + default y > + help > + Support for the StarLink-500 cache controller on StarFive platforms. > + > endmenu > diff --git a/drivers/cache/Makefile b/drivers/cache/Makefile > index 7657cff3bd6c..c515eb5714ea 100644 > --- a/drivers/cache/Makefile > +++ b/drivers/cache/Makefile > @@ -2,3 +2,4 @@ > > obj-$(CONFIG_AX45MP_L2_CACHE) += ax45mp_cache.o > obj-$(CONFIG_SIFIVE_CCACHE) += sifive_ccache.o > +obj-$(CONFIG_STARLINK_500_CACHE) += starlink500_cache.o > diff --git a/drivers/cache/starlink500_cache.c b/drivers/cache/starlink500_cache.c > new file mode 100644 > index 000000000000..eaf8303cb086 > --- /dev/null > +++ b/drivers/cache/starlink500_cache.c > @@ -0,0 +1,137 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Non-coherent cache functions for StarFive's StarLink-500 cache controller > + * > + * Copyright (C) 2024 Shanghai StarFive Technology Co., Ltd. > + * > + * Author: Joshua Yeong > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#include > + > +#define STARFIVE_SL500_CMO_FLUSH_START_ADDR 0x0 > +#define STARFIVE_SL500_CMO_FLUSH_END_ADDR 0x8 > +#define STARFIVE_SL500_CMO_FLUSH_CTL 0x10 > +#define STARFIVE_SL500_CMO_CACHE_ALIGN 0x40 > + > +#define STARFIVE_SL500_ADDRESS_RANGE_MASK GENMASK(39, 0) > +#define STARFIVE_SL500_FLUSH_CTL_MODE_MASK GENMASK(2, 1) > +#define STARFIVE_SL500_FLUSH_CTL_ENABLE_MASK BIT(0) > + > +#define STARFIVE_SL500_FLUSH_CTL_CLEAN_INVALIDATE 0 > +#define STARFIVE_SL500_FLUSH_CTL_MAKE_INVALIDATE 1 > +#define STARFIVE_SL500_FLUSH_CTL_CLEAN_SHARED 2 > + > +struct starfive_sl500_cache_priv { > + void __iomem *base_addr; > +}; > + > +static struct starfive_sl500_cache_priv starfive_sl500_cache_priv; > + > +static void starfive_sl500_cmo_flush_complete(void) > +{ > + ktime_t timeout; > + > + volatile void __iomem *_ctl = starfive_sl500_cache_priv.base_addr + > + STARFIVE_SL500_CMO_FLUSH_CTL; > + timeout = ktime_add_ms(ktime_get(), 5000); > + > + do { > + if(!(ioread64(_ctl) & STARFIVE_SL500_FLUSH_CTL_ENABLE_MASK)) > + return; > + msleep(50); These callbacks can be called from an atomic context, so you cannot use msleep() here. > + } while (ktime_before(ktime_get(), timeout)); I suggest using one of the helpers from linux/iopoll.h, e.g. readq_poll_timeout(). > + > + pr_err("StarFive CMO operation timeout\n"); > + dump_stack(); WARN or WARN_ON would be idiomatic here. > +} > + > +void starfive_sl500_dma_cache_wback(phys_addr_t paddr, unsigned long size) > +{ > + writeq(FIELD_PREP(STARFIVE_SL500_ADDRESS_RANGE_MASK, paddr), > + starfive_sl500_cache_priv.base_addr + STARFIVE_SL500_CMO_FLUSH_START_ADDR); > + writeq(FIELD_PREP(STARFIVE_SL500_ADDRESS_RANGE_MASK, paddr + size), > + starfive_sl500_cache_priv.base_addr + STARFIVE_SL500_CMO_FLUSH_END_ADDR); > + > + mb(); > + writeq(FIELD_PREP(STARFIVE_SL500_FLUSH_CTL_MODE_MASK, > + STARFIVE_SL500_FLUSH_CTL_CLEAN_SHARED), > + starfive_sl500_cache_priv.base_addr + STARFIVE_SL500_CMO_FLUSH_CTL); > + > + starfive_sl500_cmo_flush_complete(); > +} > + > +void starfive_sl500_dma_cache_invalidate(phys_addr_t paddr, unsigned long size) > +{ > + writeq(FIELD_PREP(STARFIVE_SL500_ADDRESS_RANGE_MASK, paddr), > + starfive_sl500_cache_priv.base_addr + STARFIVE_SL500_CMO_FLUSH_START_ADDR); > + writeq(FIELD_PREP(STARFIVE_SL500_ADDRESS_RANGE_MASK, paddr + size), > + starfive_sl500_cache_priv.base_addr + STARFIVE_SL500_CMO_FLUSH_END_ADDR); > + > + mb(); > + writeq(FIELD_PREP(STARFIVE_SL500_FLUSH_CTL_MODE_MASK, > + STARFIVE_SL500_FLUSH_CTL_MAKE_INVALIDATE), > + starfive_sl500_cache_priv.base_addr + STARFIVE_SL500_CMO_FLUSH_CTL); > + > + starfive_sl500_cmo_flush_complete(); > +} > + > +void starfive_sl500_dma_cache_wback_inv(phys_addr_t paddr, unsigned long size) > +{ > + writeq(FIELD_PREP(STARFIVE_SL500_ADDRESS_RANGE_MASK, paddr), > + starfive_sl500_cache_priv.base_addr + STARFIVE_SL500_CMO_FLUSH_START_ADDR); > + writeq(FIELD_PREP(STARFIVE_SL500_ADDRESS_RANGE_MASK, paddr + size), > + starfive_sl500_cache_priv.base_addr + STARFIVE_SL500_CMO_FLUSH_END_ADDR); > + > + mb(); > + writeq(FIELD_PREP(STARFIVE_SL500_FLUSH_CTL_MODE_MASK, > + STARFIVE_SL500_FLUSH_CTL_CLEAN_INVALIDATE), > + starfive_sl500_cache_priv.base_addr + STARFIVE_SL500_CMO_FLUSH_CTL); > + > + starfive_sl500_cmo_flush_complete(); > +} > + > +static const struct riscv_nonstd_cache_ops starfive_sl500_cmo_ops = { > + .wback = &starfive_sl500_dma_cache_wback, > + .inv = &starfive_sl500_dma_cache_invalidate, > + .wback_inv = &starfive_sl500_dma_cache_wback_inv, > +}; > + > +static const struct of_device_id starfive_sl500_cache_ids[] = { > + { .compatible = "starfive,starlink-500-cache" }, > + { /* sentinel */ } > +}; > + > +static int __init starfive_sl500_cache_init(void) > +{ > + struct device_node *np; > + struct resource res; > + int ret; > + > + np = of_find_matching_node(NULL, starfive_sl500_cache_ids); > + if (!of_device_is_available(np)) > + return -ENODEV; > + > + ret = of_address_to_resource(np, 0, &res); > + if (ret) > + return ret; > + > + starfive_sl500_cache_priv.base_addr = ioremap(res.start, resource_size(&res)); > + if (!starfive_sl500_cache_priv.base_addr) > + return -ENOMEM; of_address_to_resource() + ioremap() simplifies to of_iomap(). Regards, Samuel > + > + riscv_noncoherent_register_cache_ops(&starfive_sl500_cmo_ops); > + > + return 0; > +} > +early_initcall(starfive_sl500_cache_init); _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv