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From: Randy Dunlap <rdunlap@infradead.org>
To: Atish Patra <atishp@atishpatra.org>, linux-kernel@vger.kernel.org
Cc: Atish Patra <atishp@rivosinc.com>,
	Alexandre Ghiti <alex@ghiti.fr>, Anup Patel <anup.patel@wdc.com>,
	Greentime Hu <greentime.hu@sifive.com>,
	Guo Ren <guoren@linux.alibaba.com>,
	Heinrich Schuchardt <xypron.glpk@gmx.de>,
	Ingo Molnar <mingo@kernel.org>,
	Jisheng Zhang <jszhang@kernel.org>,
	kvm-riscv@lists.infradead.org, kvm@vger.kernel.org,
	linux-riscv@lists.infradead.org, Marc Zyngier <maz@kernel.org>,
	Nanyong Sun <sunnanyong@huawei.com>,
	Nick Kossifidis <mick@ics.forth.gr>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Pekka Enberg <penberg@kernel.org>,
	Vincent Chen <vincent.chen@sifive.com>,
	Vitaly Wool <vitaly.wool@konsulko.com>
Subject: Re: [RFC 5/6] RISC-V: Move spinwait booting method to its own config
Date: Fri, 3 Dec 2021 16:40:26 -0800	[thread overview]
Message-ID: <d88c18e4-b2d6-e071-7007-bb5f2b5a042c@infradead.org> (raw)
In-Reply-To: <20211204002038.113653-6-atishp@atishpatra.org>

Hi--

On 12/3/21 16:20, Atish Patra wrote:
> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> index 821252b65f89..4afb42d5707d 100644
> --- a/arch/riscv/Kconfig
> +++ b/arch/riscv/Kconfig
> @@ -403,6 +403,20 @@ config RISCV_SBI_V01
>  	  This config allows kernel to use SBI v0.1 APIs. This will be
>  	  deprecated in future once legacy M-mode software are no longer in use.
>  
> +config RISCV_BOOT_SPINWAIT
> +	bool "Spinwait booting method"
> +	depends on SMP
> +	default y
> +	help
> +	  This enables support for booting Linux via spinwait method. In the
> +	  spinwait method, all cores randomly jump to Linux. One of the core

	                                                                cores

> +	  gets chosen via lottery and all other keeps spinning on a percpu

	                                  others keep

> +	  variable. This method can not support cpu hotplug and sparse hartid

	                        cannot support CPU hotplug and sparse hartid

> +	  scheme. It should be only enabled for M-mode Linux or platforms relying
> +	  on older firmware without SBI HSM extension. All other platform should

	                                                         platforms

> +	  rely on ordered booing via SBI HSM extension which gets chosen

	                  booting

> +          dynamically at runtime if the firmware supports it.

	  dynamically at runtime if the firmware supports it.

(Last line should be indented with tab + 2 spaces, not 10 spaces.)


-- 
~Randy

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  reply	other threads:[~2021-12-04  0:40 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-12-04  0:20 [RFC 0/6] Sparse HART id support Atish Patra
2021-12-04  0:20 ` [RFC 1/6] RISC-V: Avoid using per cpu array for ordered booting Atish Patra
2021-12-13 12:48   ` Anup Patel
2021-12-13 21:05     ` Atish Patra
2021-12-04  0:20 ` [RFC 2/6] RISC-V: Do not print the SBI version during HSM extension boot print Atish Patra
2021-12-13 12:49   ` Anup Patel
2021-12-04  0:20 ` [RFC 3/6] RISC-V: Use __cpu_up_stack/task_pointer only for spinwait method Atish Patra
2021-12-13 12:50   ` Anup Patel
2021-12-13 12:59   ` Marc Zyngier
2021-12-13 21:12     ` Atish Patra
2021-12-04  0:20 ` [RFC 4/6] RISC-V: Move the entire hart selection via lottery to SMP Atish Patra
2021-12-13 12:57   ` Anup Patel
2021-12-04  0:20 ` [RFC 5/6] RISC-V: Move spinwait booting method to its own config Atish Patra
2021-12-04  0:40   ` Randy Dunlap [this message]
2021-12-13 13:01   ` Anup Patel
2021-12-13 21:08     ` Atish Patra
2021-12-04  0:20 ` [RFC 6/6] RISC-V: Do not use cpumask data structure for hartid bitmap Atish Patra
2021-12-06 15:28 ` [RFC 0/6] Sparse HART id support Rob Herring
2021-12-13 21:27   ` Atish Patra
2021-12-13 23:11     ` Rob Herring
2021-12-14  0:58       ` Atish Patra

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