* [PATCH 0/7] Initial device tree support for StarFive JH8100 SoC
@ 2023-11-27 1:35 Sia Jee Heng
2023-11-27 1:35 ` [PATCH 1/7] dt-bindings: riscv: Add StarFive Dubhe compatibles Sia Jee Heng
` (6 more replies)
0 siblings, 7 replies; 24+ messages in thread
From: Sia Jee Heng @ 2023-11-27 1:35 UTC (permalink / raw)
To: paul.walmsley, palmer, aou, conor, kernel, robh+dt,
emil.renner.berthing
Cc: linux-riscv, linux-kernel, jeeheng.sia, leyfoon.tan
StarFive JH8100 SoC consists of 4 RISC-V performance Cores (Dubhe-90) and
2 RISC-V energy efficient cores (Dubhe-80). It also features various
interfaces such as DDR4, Gbit-Ether, CAN, USB 3.2, SD/MMC, etc., making it
ideal for high-performance computing scenarios.
This patch series introduces initial SoC DTSI support for the StarFive
JH8100 SoC. The relevant dt-binding documentation has been updated
accordingly. Below is the list of IP blocks added in the initial SoC DTSI,
which can be used for booting via initramfs on FPGA:
- StarFive Dubhe-80 CPU
- StarFive Dubhe-90 CPU
- PLIC
- CLINT
- UART
The primary goal is to include foundational patches so that additional
drivers can be built on top of this framework.
Sia Jee Heng (7):
dt-bindings: riscv: Add StarFive Dubhe compatibles
dt-bindings: riscv: Add StarFive JH8100 SoC
dt-bindings: timer: Add StarFive JH8100 clint
dt-bindings: interrupt-controller: Add StarFive JH8100 plic
dt-bindings: xilinx: Add StarFive compatible string
serial: xilinx_uartps: Add new compatible string for StarFive
riscv: dts: starfive: Add initial StarFive JH8100 device tree
.../sifive,plic-1.0.0.yaml | 1 +
.../devicetree/bindings/riscv/cpus.yaml | 2 +
.../devicetree/bindings/riscv/starfive.yaml | 5 +-
.../devicetree/bindings/serial/cdns,uart.yaml | 3 +
.../bindings/timer/sifive,clint.yaml | 1 +
arch/riscv/boot/dts/starfive/Makefile | 1 +
arch/riscv/boot/dts/starfive/jh8100-evb.dts | 42 ++
arch/riscv/boot/dts/starfive/jh8100.dtsi | 365 ++++++++++++++++++
drivers/tty/serial/xilinx_uartps.c | 3 +-
9 files changed, 421 insertions(+), 2 deletions(-)
create mode 100644 arch/riscv/boot/dts/starfive/jh8100-evb.dts
create mode 100644 arch/riscv/boot/dts/starfive/jh8100.dtsi
base-commit: d2da77f431ac49b5763b88751a75f70daa46296c
--
2.34.1
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^ permalink raw reply [flat|nested] 24+ messages in thread* [PATCH 1/7] dt-bindings: riscv: Add StarFive Dubhe compatibles 2023-11-27 1:35 [PATCH 0/7] Initial device tree support for StarFive JH8100 SoC Sia Jee Heng @ 2023-11-27 1:35 ` Sia Jee Heng 2023-11-27 8:47 ` Krzysztof Kozlowski 2023-11-27 1:35 ` [PATCH 2/7] dt-bindings: riscv: Add StarFive JH8100 SoC Sia Jee Heng ` (5 subsequent siblings) 6 siblings, 1 reply; 24+ messages in thread From: Sia Jee Heng @ 2023-11-27 1:35 UTC (permalink / raw) To: paul.walmsley, palmer, aou, conor, kernel, robh+dt, emil.renner.berthing Cc: linux-riscv, linux-kernel, jeeheng.sia, leyfoon.tan Dubhe-80 and Dubhe-90 are RISC-V cpu core from StarFive Technology. Signed-off-by: Sia Jee Heng <jeeheng.sia@starfivetech.com> Reviewed-by: Ley Foon Tan <leyfoon.tan@starfivetech.com> --- Documentation/devicetree/bindings/riscv/cpus.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index f392e367d673..493972b29a22 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -48,6 +48,8 @@ properties: - thead,c906 - thead,c910 - thead,c920 + - starfive,dubhe-80 + - starfive,dubhe-90 - const: riscv - items: - enum: -- 2.34.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply related [flat|nested] 24+ messages in thread
* Re: [PATCH 1/7] dt-bindings: riscv: Add StarFive Dubhe compatibles 2023-11-27 1:35 ` [PATCH 1/7] dt-bindings: riscv: Add StarFive Dubhe compatibles Sia Jee Heng @ 2023-11-27 8:47 ` Krzysztof Kozlowski 0 siblings, 0 replies; 24+ messages in thread From: Krzysztof Kozlowski @ 2023-11-27 8:47 UTC (permalink / raw) To: Sia Jee Heng, paul.walmsley, palmer, aou, conor, kernel, robh+dt, emil.renner.berthing Cc: linux-riscv, linux-kernel, leyfoon.tan On 27/11/2023 02:35, Sia Jee Heng wrote: > Dubhe-80 and Dubhe-90 are RISC-V cpu core from StarFive Technology. > > Signed-off-by: Sia Jee Heng <jeeheng.sia@starfivetech.com> > Reviewed-by: Ley Foon Tan <leyfoon.tan@starfivetech.com> Please use scripts/get_maintainers.pl to get a list of necessary people and lists to CC. It might happen, that command when run on an older kernel, gives you outdated entries. Therefore please be sure you base your patches on recent Linux kernel. You missed at least devicetree list (maybe more), so this won't be tested by automated tooling. Performing review on untested code might be a waste of time, thus I will skip this patch entirely till you follow the process allowing the patch to be tested. Please kindly resend and include all necessary To/Cc entries. Best regards, Krzysztof _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH 2/7] dt-bindings: riscv: Add StarFive JH8100 SoC 2023-11-27 1:35 [PATCH 0/7] Initial device tree support for StarFive JH8100 SoC Sia Jee Heng 2023-11-27 1:35 ` [PATCH 1/7] dt-bindings: riscv: Add StarFive Dubhe compatibles Sia Jee Heng @ 2023-11-27 1:35 ` Sia Jee Heng 2023-11-27 1:35 ` [PATCH 3/7] dt-bindings: timer: Add StarFive JH8100 clint Sia Jee Heng ` (4 subsequent siblings) 6 siblings, 0 replies; 24+ messages in thread From: Sia Jee Heng @ 2023-11-27 1:35 UTC (permalink / raw) To: paul.walmsley, palmer, aou, conor, kernel, robh+dt, emil.renner.berthing Cc: linux-riscv, linux-kernel, jeeheng.sia, leyfoon.tan Add device tree bindings for the StarFive JH8100 RISC-V SoC Signed-off-by: Sia Jee Heng <jeeheng.sia@starfivetech.com> Reviewed-by: Ley Foon Tan <leyfoon.tan@starfivetech.com> --- Documentation/devicetree/bindings/riscv/starfive.yaml | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/riscv/starfive.yaml b/Documentation/devicetree/bindings/riscv/starfive.yaml index cc4d92f0a1bf..7e2da9eef3db 100644 --- a/Documentation/devicetree/bindings/riscv/starfive.yaml +++ b/Documentation/devicetree/bindings/riscv/starfive.yaml @@ -29,7 +29,10 @@ properties: - starfive,visionfive-2-v1.2a - starfive,visionfive-2-v1.3b - const: starfive,jh7110 - + - items: + - enum: + - starfive,jh8100-evb + - const: starfive,jh8100 additionalProperties: true ... -- 2.34.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH 3/7] dt-bindings: timer: Add StarFive JH8100 clint 2023-11-27 1:35 [PATCH 0/7] Initial device tree support for StarFive JH8100 SoC Sia Jee Heng 2023-11-27 1:35 ` [PATCH 1/7] dt-bindings: riscv: Add StarFive Dubhe compatibles Sia Jee Heng 2023-11-27 1:35 ` [PATCH 2/7] dt-bindings: riscv: Add StarFive JH8100 SoC Sia Jee Heng @ 2023-11-27 1:35 ` Sia Jee Heng 2023-11-27 8:47 ` Krzysztof Kozlowski 2023-11-27 1:35 ` [PATCH 4/7] dt-bindings: interrupt-controller: Add StarFive JH8100 plic Sia Jee Heng ` (3 subsequent siblings) 6 siblings, 1 reply; 24+ messages in thread From: Sia Jee Heng @ 2023-11-27 1:35 UTC (permalink / raw) To: paul.walmsley, palmer, aou, conor, kernel, robh+dt, emil.renner.berthing Cc: linux-riscv, linux-kernel, jeeheng.sia, leyfoon.tan Add compatible string for the StarFive JH8100 clint Signed-off-by: Sia Jee Heng <jeeheng.sia@starfivetech.com> Reviewed-by: Ley Foon Tan <leyfoon.tan@starfivetech.com> --- Documentation/devicetree/bindings/timer/sifive,clint.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml index e8be6c470364..01254261e156 100644 --- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml @@ -33,6 +33,7 @@ properties: - sifive,fu540-c000-clint # SiFive FU540 - starfive,jh7100-clint # StarFive JH7100 - starfive,jh7110-clint # StarFive JH7110 + - starfive,jh8100-clint # StarFive JH8100 - const: sifive,clint0 # SiFive CLINT v0 IP block - items: - enum: -- 2.34.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply related [flat|nested] 24+ messages in thread
* Re: [PATCH 3/7] dt-bindings: timer: Add StarFive JH8100 clint 2023-11-27 1:35 ` [PATCH 3/7] dt-bindings: timer: Add StarFive JH8100 clint Sia Jee Heng @ 2023-11-27 8:47 ` Krzysztof Kozlowski 2023-11-28 5:24 ` JeeHeng Sia 0 siblings, 1 reply; 24+ messages in thread From: Krzysztof Kozlowski @ 2023-11-27 8:47 UTC (permalink / raw) To: Sia Jee Heng, paul.walmsley, palmer, aou, conor, kernel, robh+dt, emil.renner.berthing Cc: linux-riscv, linux-kernel, leyfoon.tan On 27/11/2023 02:35, Sia Jee Heng wrote: > Add compatible string for the StarFive JH8100 clint > > Signed-off-by: Sia Jee Heng <jeeheng.sia@starfivetech.com> > Reviewed-by: Ley Foon Tan <leyfoon.tan@starfivetech.com> > --- Please use scripts/get_maintainers.pl to get a list of necessary people and lists to CC. It might happen, that command when run on an older kernel, gives you outdated entries. Therefore please be sure you base your patches on recent Linux kernel. You missed at least devicetree list (maybe more), so this won't be tested by automated tooling. Performing review on untested code might be a waste of time, thus I will skip this patch entirely till you follow the process allowing the patch to be tested. Please kindly resend and include all necessary To/Cc entries. Best regards, Krzysztof _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply [flat|nested] 24+ messages in thread
* RE: [PATCH 3/7] dt-bindings: timer: Add StarFive JH8100 clint 2023-11-27 8:47 ` Krzysztof Kozlowski @ 2023-11-28 5:24 ` JeeHeng Sia 2023-11-28 7:19 ` Krzysztof Kozlowski 0 siblings, 1 reply; 24+ messages in thread From: JeeHeng Sia @ 2023-11-28 5:24 UTC (permalink / raw) To: Krzysztof Kozlowski, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, conor@kernel.org, kernel@esmil.dk, robh+dt@kernel.org, emil.renner.berthing@canonical.com Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Leyfoon Tan > -----Original Message----- > From: Krzysztof Kozlowski <krzk@kernel.org> > Sent: Monday, November 27, 2023 4:48 PM > To: JeeHeng Sia <jeeheng.sia@starfivetech.com>; paul.walmsley@sifive.com; palmer@dabbelt.com; aou@eecs.berkeley.edu; > conor@kernel.org; kernel@esmil.dk; robh+dt@kernel.org; emil.renner.berthing@canonical.com > Cc: linux-riscv@lists.infradead.org; linux-kernel@vger.kernel.org; Leyfoon Tan <leyfoon.tan@starfivetech.com> > Subject: Re: [PATCH 3/7] dt-bindings: timer: Add StarFive JH8100 clint > > On 27/11/2023 02:35, Sia Jee Heng wrote: > > Add compatible string for the StarFive JH8100 clint > > > > Signed-off-by: Sia Jee Heng <jeeheng.sia@starfivetech.com> > > Reviewed-by: Ley Foon Tan <leyfoon.tan@starfivetech.com> > > --- > > Please use scripts/get_maintainers.pl to get a list of necessary people > and lists to CC. It might happen, that command when run on an older > kernel, gives you outdated entries. Therefore please be sure you base > your patches on recent Linux kernel. > > You missed at least devicetree list (maybe more), so this won't be > tested by automated tooling. Performing review on untested code might be > a waste of time, thus I will skip this patch entirely till you follow > the process allowing the patch to be tested. > > Please kindly resend and include all necessary To/Cc entries. Noted. Should I resend the patches with the V1 tag and with addressed comments? > > Best regards, > Krzysztof _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH 3/7] dt-bindings: timer: Add StarFive JH8100 clint 2023-11-28 5:24 ` JeeHeng Sia @ 2023-11-28 7:19 ` Krzysztof Kozlowski 2023-11-28 7:56 ` JeeHeng Sia 0 siblings, 1 reply; 24+ messages in thread From: Krzysztof Kozlowski @ 2023-11-28 7:19 UTC (permalink / raw) To: JeeHeng Sia, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, conor@kernel.org, kernel@esmil.dk, robh+dt@kernel.org, emil.renner.berthing@canonical.com Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Leyfoon Tan On 28/11/2023 06:24, JeeHeng Sia wrote: > > >> -----Original Message----- >> From: Krzysztof Kozlowski <krzk@kernel.org> >> Sent: Monday, November 27, 2023 4:48 PM >> To: JeeHeng Sia <jeeheng.sia@starfivetech.com>; paul.walmsley@sifive.com; palmer@dabbelt.com; aou@eecs.berkeley.edu; >> conor@kernel.org; kernel@esmil.dk; robh+dt@kernel.org; emil.renner.berthing@canonical.com >> Cc: linux-riscv@lists.infradead.org; linux-kernel@vger.kernel.org; Leyfoon Tan <leyfoon.tan@starfivetech.com> >> Subject: Re: [PATCH 3/7] dt-bindings: timer: Add StarFive JH8100 clint >> >> On 27/11/2023 02:35, Sia Jee Heng wrote: >>> Add compatible string for the StarFive JH8100 clint >>> >>> Signed-off-by: Sia Jee Heng <jeeheng.sia@starfivetech.com> >>> Reviewed-by: Ley Foon Tan <leyfoon.tan@starfivetech.com> >>> --- >> >> Please use scripts/get_maintainers.pl to get a list of necessary people >> and lists to CC. It might happen, that command when run on an older >> kernel, gives you outdated entries. Therefore please be sure you base >> your patches on recent Linux kernel. >> >> You missed at least devicetree list (maybe more), so this won't be >> tested by automated tooling. Performing review on untested code might be >> a waste of time, thus I will skip this patch entirely till you follow >> the process allowing the patch to be tested. >> >> Please kindly resend and include all necessary To/Cc entries. > Noted. Should I resend the patches with the V1 tag and with addressed comments? This was v1. Next one is v2. Best regards, Krzysztof _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply [flat|nested] 24+ messages in thread
* RE: [PATCH 3/7] dt-bindings: timer: Add StarFive JH8100 clint 2023-11-28 7:19 ` Krzysztof Kozlowski @ 2023-11-28 7:56 ` JeeHeng Sia 0 siblings, 0 replies; 24+ messages in thread From: JeeHeng Sia @ 2023-11-28 7:56 UTC (permalink / raw) To: Krzysztof Kozlowski, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, conor@kernel.org, kernel@esmil.dk, robh+dt@kernel.org, emil.renner.berthing@canonical.com Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Leyfoon Tan > -----Original Message----- > From: Krzysztof Kozlowski <krzk@kernel.org> > Sent: Tuesday, November 28, 2023 3:20 PM > To: JeeHeng Sia <jeeheng.sia@starfivetech.com>; paul.walmsley@sifive.com; palmer@dabbelt.com; aou@eecs.berkeley.edu; > conor@kernel.org; kernel@esmil.dk; robh+dt@kernel.org; emil.renner.berthing@canonical.com > Cc: linux-riscv@lists.infradead.org; linux-kernel@vger.kernel.org; Leyfoon Tan <leyfoon.tan@starfivetech.com> > Subject: Re: [PATCH 3/7] dt-bindings: timer: Add StarFive JH8100 clint > > On 28/11/2023 06:24, JeeHeng Sia wrote: > > > > > >> -----Original Message----- > >> From: Krzysztof Kozlowski <krzk@kernel.org> > >> Sent: Monday, November 27, 2023 4:48 PM > >> To: JeeHeng Sia <jeeheng.sia@starfivetech.com>; paul.walmsley@sifive.com; palmer@dabbelt.com; aou@eecs.berkeley.edu; > >> conor@kernel.org; kernel@esmil.dk; robh+dt@kernel.org; emil.renner.berthing@canonical.com > >> Cc: linux-riscv@lists.infradead.org; linux-kernel@vger.kernel.org; Leyfoon Tan <leyfoon.tan@starfivetech.com> > >> Subject: Re: [PATCH 3/7] dt-bindings: timer: Add StarFive JH8100 clint > >> > >> On 27/11/2023 02:35, Sia Jee Heng wrote: > >>> Add compatible string for the StarFive JH8100 clint > >>> > >>> Signed-off-by: Sia Jee Heng <jeeheng.sia@starfivetech.com> > >>> Reviewed-by: Ley Foon Tan <leyfoon.tan@starfivetech.com> > >>> --- > >> > >> Please use scripts/get_maintainers.pl to get a list of necessary people > >> and lists to CC. It might happen, that command when run on an older > >> kernel, gives you outdated entries. Therefore please be sure you base > >> your patches on recent Linux kernel. > >> > >> You missed at least devicetree list (maybe more), so this won't be > >> tested by automated tooling. Performing review on untested code might be > >> a waste of time, thus I will skip this patch entirely till you follow > >> the process allowing the patch to be tested. > >> > >> Please kindly resend and include all necessary To/Cc entries. > > Noted. Should I resend the patches with the V1 tag and with addressed comments? > > This was v1. Next one is v2. Noted with thanks. > > Best regards, > Krzysztof _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH 4/7] dt-bindings: interrupt-controller: Add StarFive JH8100 plic 2023-11-27 1:35 [PATCH 0/7] Initial device tree support for StarFive JH8100 SoC Sia Jee Heng ` (2 preceding siblings ...) 2023-11-27 1:35 ` [PATCH 3/7] dt-bindings: timer: Add StarFive JH8100 clint Sia Jee Heng @ 2023-11-27 1:35 ` Sia Jee Heng 2023-11-27 8:48 ` Krzysztof Kozlowski 2023-11-27 1:36 ` [PATCH 5/7] dt-bindings: xilinx: Add StarFive compatible string Sia Jee Heng ` (2 subsequent siblings) 6 siblings, 1 reply; 24+ messages in thread From: Sia Jee Heng @ 2023-11-27 1:35 UTC (permalink / raw) To: paul.walmsley, palmer, aou, conor, kernel, robh+dt, emil.renner.berthing Cc: linux-riscv, linux-kernel, jeeheng.sia, leyfoon.tan Add compatible string for StarFive JH8100 plic Signed-off-by: Sia Jee Heng <jeeheng.sia@starfivetech.com> Reviewed-by: Ley Foon Tan <leyfoon.tan@starfivetech.com> --- .../bindings/interrupt-controller/sifive,plic-1.0.0.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml index 0c07e8dda445..8f5c6044cef7 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml @@ -61,6 +61,7 @@ properties: - sifive,fu540-c000-plic - starfive,jh7100-plic - starfive,jh7110-plic + - starfive,jh8100-plic - const: sifive,plic-1.0.0 - items: - enum: -- 2.34.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply related [flat|nested] 24+ messages in thread
* Re: [PATCH 4/7] dt-bindings: interrupt-controller: Add StarFive JH8100 plic 2023-11-27 1:35 ` [PATCH 4/7] dt-bindings: interrupt-controller: Add StarFive JH8100 plic Sia Jee Heng @ 2023-11-27 8:48 ` Krzysztof Kozlowski 0 siblings, 0 replies; 24+ messages in thread From: Krzysztof Kozlowski @ 2023-11-27 8:48 UTC (permalink / raw) To: Sia Jee Heng, paul.walmsley, palmer, aou, conor, kernel, robh+dt, emil.renner.berthing Cc: linux-riscv, linux-kernel, leyfoon.tan On 27/11/2023 02:35, Sia Jee Heng wrote: > Add compatible string for StarFive JH8100 plic > > Signed-off-by: Sia Jee Heng <jeeheng.sia@starfivetech.com> > Reviewed-by: Ley Foon Tan <leyfoon.tan@starfivetech.com> > --- Please use scripts/get_maintainers.pl to get a list of necessary people and lists to CC. It might happen, that command when run on an older kernel, gives you outdated entries. Therefore please be sure you base your patches on recent Linux kernel. You missed at least devicetree list (maybe more), so this won't be tested by automated tooling. Performing review on untested code might be a waste of time, thus I will skip this patch entirely till you follow the process allowing the patch to be tested. Please kindly resend and include all necessary To/Cc entries. Best regards, Krzysztof _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH 5/7] dt-bindings: xilinx: Add StarFive compatible string 2023-11-27 1:35 [PATCH 0/7] Initial device tree support for StarFive JH8100 SoC Sia Jee Heng ` (3 preceding siblings ...) 2023-11-27 1:35 ` [PATCH 4/7] dt-bindings: interrupt-controller: Add StarFive JH8100 plic Sia Jee Heng @ 2023-11-27 1:36 ` Sia Jee Heng 2023-11-27 8:48 ` Krzysztof Kozlowski 2023-11-27 1:36 ` [PATCH 6/7] serial: xilinx_uartps: Add new compatible string for StarFive Sia Jee Heng 2023-11-27 1:36 ` [PATCH 7/7] riscv: dts: starfive: Add initial StarFive JH8100 device tree Sia Jee Heng 6 siblings, 1 reply; 24+ messages in thread From: Sia Jee Heng @ 2023-11-27 1:36 UTC (permalink / raw) To: paul.walmsley, palmer, aou, conor, kernel, robh+dt, emil.renner.berthing Cc: linux-riscv, linux-kernel, jeeheng.sia, leyfoon.tan Add starfive,jh8100-uart compatible string Signed-off-by: Sia Jee Heng <jeeheng.sia@starfivetech.com> Reviewed-by: Ley Foon Tan <leyfoon.tan@starfivetech.com> --- Documentation/devicetree/bindings/serial/cdns,uart.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/serial/cdns,uart.yaml b/Documentation/devicetree/bindings/serial/cdns,uart.yaml index e35ad1109efc..254373cb1ac7 100644 --- a/Documentation/devicetree/bindings/serial/cdns,uart.yaml +++ b/Documentation/devicetree/bindings/serial/cdns,uart.yaml @@ -20,6 +20,9 @@ properties: items: - const: xlnx,zynqmp-uart - const: cdns,uart-r1p12 + - description: UART controller for StarFive JH8100 SoC + items: + - const: starfive,jh8100-uart reg: maxItems: 1 -- 2.34.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply related [flat|nested] 24+ messages in thread
* Re: [PATCH 5/7] dt-bindings: xilinx: Add StarFive compatible string 2023-11-27 1:36 ` [PATCH 5/7] dt-bindings: xilinx: Add StarFive compatible string Sia Jee Heng @ 2023-11-27 8:48 ` Krzysztof Kozlowski 2023-11-28 5:24 ` JeeHeng Sia 0 siblings, 1 reply; 24+ messages in thread From: Krzysztof Kozlowski @ 2023-11-27 8:48 UTC (permalink / raw) To: Sia Jee Heng, paul.walmsley, palmer, aou, conor, kernel, robh+dt, emil.renner.berthing Cc: linux-riscv, linux-kernel, leyfoon.tan On 27/11/2023 02:36, Sia Jee Heng wrote: > Add starfive,jh8100-uart compatible string Describe the hardware. Why is it in xilinx? Also, missing full stop in each commit msg. > > Signed-off-by: Sia Jee Heng <jeeheng.sia@starfivetech.com> > Reviewed-by: Ley Foon Tan <leyfoon.tan@starfivetech.com> > --- Please use scripts/get_maintainers.pl to get a list of necessary people and lists to CC. It might happen, that command when run on an older kernel, gives you outdated entries. Therefore please be sure you base your patches on recent Linux kernel. You missed at least devicetree list (maybe more), so this won't be tested by automated tooling. Performing review on untested code might be a waste of time, thus I will skip this patch entirely till you follow the process allowing the patch to be tested. Please kindly resend and include all necessary To/Cc entries. Best regards, Krzysztof _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply [flat|nested] 24+ messages in thread
* RE: [PATCH 5/7] dt-bindings: xilinx: Add StarFive compatible string 2023-11-27 8:48 ` Krzysztof Kozlowski @ 2023-11-28 5:24 ` JeeHeng Sia 0 siblings, 0 replies; 24+ messages in thread From: JeeHeng Sia @ 2023-11-28 5:24 UTC (permalink / raw) To: Krzysztof Kozlowski, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, conor@kernel.org, kernel@esmil.dk, robh+dt@kernel.org, emil.renner.berthing@canonical.com Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Leyfoon Tan > -----Original Message----- > From: Krzysztof Kozlowski <krzk@kernel.org> > Sent: Monday, November 27, 2023 4:49 PM > To: JeeHeng Sia <jeeheng.sia@starfivetech.com>; paul.walmsley@sifive.com; palmer@dabbelt.com; aou@eecs.berkeley.edu; > conor@kernel.org; kernel@esmil.dk; robh+dt@kernel.org; emil.renner.berthing@canonical.com > Cc: linux-riscv@lists.infradead.org; linux-kernel@vger.kernel.org; Leyfoon Tan <leyfoon.tan@starfivetech.com> > Subject: Re: [PATCH 5/7] dt-bindings: xilinx: Add StarFive compatible string > > On 27/11/2023 02:36, Sia Jee Heng wrote: > > Add starfive,jh8100-uart compatible string > > Describe the hardware. Why is it in xilinx? My bad. It should CDNS UART driver. Will fix it. > > Also, missing full stop in each commit msg. Noted. > > > > > Signed-off-by: Sia Jee Heng <jeeheng.sia@starfivetech.com> > > Reviewed-by: Ley Foon Tan <leyfoon.tan@starfivetech.com> > > --- > > Please use scripts/get_maintainers.pl to get a list of necessary people > and lists to CC. It might happen, that command when run on an older > kernel, gives you outdated entries. Therefore please be sure you base > your patches on recent Linux kernel. > > You missed at least devicetree list (maybe more), so this won't be > tested by automated tooling. Performing review on untested code might be > a waste of time, thus I will skip this patch entirely till you follow > the process allowing the patch to be tested. > > Please kindly resend and include all necessary To/Cc entries. Noted. Should I resend the patches with the V1 tag and with addressed comments? > > Best regards, > Krzysztof _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH 6/7] serial: xilinx_uartps: Add new compatible string for StarFive 2023-11-27 1:35 [PATCH 0/7] Initial device tree support for StarFive JH8100 SoC Sia Jee Heng ` (4 preceding siblings ...) 2023-11-27 1:36 ` [PATCH 5/7] dt-bindings: xilinx: Add StarFive compatible string Sia Jee Heng @ 2023-11-27 1:36 ` Sia Jee Heng 2023-11-27 8:49 ` Krzysztof Kozlowski 2023-11-27 1:36 ` [PATCH 7/7] riscv: dts: starfive: Add initial StarFive JH8100 device tree Sia Jee Heng 6 siblings, 1 reply; 24+ messages in thread From: Sia Jee Heng @ 2023-11-27 1:36 UTC (permalink / raw) To: paul.walmsley, palmer, aou, conor, kernel, robh+dt, emil.renner.berthing Cc: linux-riscv, linux-kernel, jeeheng.sia, leyfoon.tan This patch adds the new compatible string for StarFive JH8100 SoC Signed-off-by: Sia Jee Heng <jeeheng.sia@starfivetech.com> Reviewed-by: Ley Foon Tan <leyfoon.tan@starfivetech.com> --- drivers/tty/serial/xilinx_uartps.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/tty/serial/xilinx_uartps.c b/drivers/tty/serial/xilinx_uartps.c index 66a45a634158..170901c143c2 100644 --- a/drivers/tty/serial/xilinx_uartps.c +++ b/drivers/tty/serial/xilinx_uartps.c @@ -1210,7 +1210,7 @@ OF_EARLYCON_DECLARE(cdns, "xlnx,xuartps", cdns_early_console_setup); OF_EARLYCON_DECLARE(cdns, "cdns,uart-r1p8", cdns_early_console_setup); OF_EARLYCON_DECLARE(cdns, "cdns,uart-r1p12", cdns_early_console_setup); OF_EARLYCON_DECLARE(cdns, "xlnx,zynqmp-uart", cdns_early_console_setup); - +OF_EARLYCON_DECLARE(cdns, "starfive,jh8100-uart", cdns_early_console_setup); /* Static pointer to console port */ static struct uart_port *console_port; @@ -1448,6 +1448,7 @@ static const struct of_device_id cdns_uart_of_match[] = { { .compatible = "cdns,uart-r1p8", }, { .compatible = "cdns,uart-r1p12", .data = &zynqmp_uart_def }, { .compatible = "xlnx,zynqmp-uart", .data = &zynqmp_uart_def }, + { .compatible = "starfive,jh8100-uart", }, {} }; MODULE_DEVICE_TABLE(of, cdns_uart_of_match); -- 2.34.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply related [flat|nested] 24+ messages in thread
* Re: [PATCH 6/7] serial: xilinx_uartps: Add new compatible string for StarFive 2023-11-27 1:36 ` [PATCH 6/7] serial: xilinx_uartps: Add new compatible string for StarFive Sia Jee Heng @ 2023-11-27 8:49 ` Krzysztof Kozlowski 2023-11-28 5:25 ` JeeHeng Sia 0 siblings, 1 reply; 24+ messages in thread From: Krzysztof Kozlowski @ 2023-11-27 8:49 UTC (permalink / raw) To: Sia Jee Heng, paul.walmsley, palmer, aou, conor, kernel, robh+dt, emil.renner.berthing Cc: linux-riscv, linux-kernel, leyfoon.tan On 27/11/2023 02:36, Sia Jee Heng wrote: > This patch adds the new compatible string for StarFive JH8100 SoC > > Signed-off-by: Sia Jee Heng <jeeheng.sia@starfivetech.com> > Reviewed-by: Ley Foon Tan <leyfoon.tan@starfivetech.com> > --- > drivers/tty/serial/xilinx_uartps.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/drivers/tty/serial/xilinx_uartps.c b/drivers/tty/serial/xilinx_uartps.c > index 66a45a634158..170901c143c2 100644 > --- a/drivers/tty/serial/xilinx_uartps.c > +++ b/drivers/tty/serial/xilinx_uartps.c > @@ -1210,7 +1210,7 @@ OF_EARLYCON_DECLARE(cdns, "xlnx,xuartps", cdns_early_console_setup); > OF_EARLYCON_DECLARE(cdns, "cdns,uart-r1p8", cdns_early_console_setup); > OF_EARLYCON_DECLARE(cdns, "cdns,uart-r1p12", cdns_early_console_setup); > OF_EARLYCON_DECLARE(cdns, "xlnx,zynqmp-uart", cdns_early_console_setup); > - > +OF_EARLYCON_DECLARE(cdns, "starfive,jh8100-uart", cdns_early_console_setup); > > /* Static pointer to console port */ > static struct uart_port *console_port; > @@ -1448,6 +1448,7 @@ static const struct of_device_id cdns_uart_of_match[] = { > { .compatible = "cdns,uart-r1p8", }, > { .compatible = "cdns,uart-r1p12", .data = &zynqmp_uart_def }, > { .compatible = "xlnx,zynqmp-uart", .data = &zynqmp_uart_def }, > + { .compatible = "starfive,jh8100-uart", }, Why you do not express compatibility in your bindings? Skip this driver change. Best regards, Krzysztof _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply [flat|nested] 24+ messages in thread
* RE: [PATCH 6/7] serial: xilinx_uartps: Add new compatible string for StarFive 2023-11-27 8:49 ` Krzysztof Kozlowski @ 2023-11-28 5:25 ` JeeHeng Sia 2023-11-28 7:21 ` Krzysztof Kozlowski 0 siblings, 1 reply; 24+ messages in thread From: JeeHeng Sia @ 2023-11-28 5:25 UTC (permalink / raw) To: Krzysztof Kozlowski, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, conor@kernel.org, kernel@esmil.dk, robh+dt@kernel.org, emil.renner.berthing@canonical.com Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Leyfoon Tan > -----Original Message----- > From: Krzysztof Kozlowski <krzk@kernel.org> > Sent: Monday, November 27, 2023 4:49 PM > To: JeeHeng Sia <jeeheng.sia@starfivetech.com>; paul.walmsley@sifive.com; palmer@dabbelt.com; aou@eecs.berkeley.edu; > conor@kernel.org; kernel@esmil.dk; robh+dt@kernel.org; emil.renner.berthing@canonical.com > Cc: linux-riscv@lists.infradead.org; linux-kernel@vger.kernel.org; Leyfoon Tan <leyfoon.tan@starfivetech.com> > Subject: Re: [PATCH 6/7] serial: xilinx_uartps: Add new compatible string for StarFive > > On 27/11/2023 02:36, Sia Jee Heng wrote: > > This patch adds the new compatible string for StarFive JH8100 SoC > > > > Signed-off-by: Sia Jee Heng <jeeheng.sia@starfivetech.com> > > Reviewed-by: Ley Foon Tan <leyfoon.tan@starfivetech.com> > > --- > > drivers/tty/serial/xilinx_uartps.c | 3 ++- > > 1 file changed, 2 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/tty/serial/xilinx_uartps.c b/drivers/tty/serial/xilinx_uartps.c > > index 66a45a634158..170901c143c2 100644 > > --- a/drivers/tty/serial/xilinx_uartps.c > > +++ b/drivers/tty/serial/xilinx_uartps.c > > @@ -1210,7 +1210,7 @@ OF_EARLYCON_DECLARE(cdns, "xlnx,xuartps", cdns_early_console_setup); > > OF_EARLYCON_DECLARE(cdns, "cdns,uart-r1p8", cdns_early_console_setup); > > OF_EARLYCON_DECLARE(cdns, "cdns,uart-r1p12", cdns_early_console_setup); > > OF_EARLYCON_DECLARE(cdns, "xlnx,zynqmp-uart", cdns_early_console_setup); > > - > > +OF_EARLYCON_DECLARE(cdns, "starfive,jh8100-uart", cdns_early_console_setup); > > > > /* Static pointer to console port */ > > static struct uart_port *console_port; > > @@ -1448,6 +1448,7 @@ static const struct of_device_id cdns_uart_of_match[] = { > > { .compatible = "cdns,uart-r1p8", }, > > { .compatible = "cdns,uart-r1p12", .data = &zynqmp_uart_def }, > > { .compatible = "xlnx,zynqmp-uart", .data = &zynqmp_uart_def }, > > + { .compatible = "starfive,jh8100-uart", }, > > Why you do not express compatibility in your bindings? Skip this driver > change. The compatibility string was added to the binding in the 5th patch. We need to add this compatibility string to the driver, as the other compatibilities were used for other SoCs. > > Best regards, > Krzysztof _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH 6/7] serial: xilinx_uartps: Add new compatible string for StarFive 2023-11-28 5:25 ` JeeHeng Sia @ 2023-11-28 7:21 ` Krzysztof Kozlowski 2023-11-28 7:57 ` JeeHeng Sia 0 siblings, 1 reply; 24+ messages in thread From: Krzysztof Kozlowski @ 2023-11-28 7:21 UTC (permalink / raw) To: JeeHeng Sia, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, conor@kernel.org, kernel@esmil.dk, robh+dt@kernel.org, emil.renner.berthing@canonical.com Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Leyfoon Tan On 28/11/2023 06:25, JeeHeng Sia wrote: > > >> -----Original Message----- >> From: Krzysztof Kozlowski <krzk@kernel.org> >> Sent: Monday, November 27, 2023 4:49 PM >> To: JeeHeng Sia <jeeheng.sia@starfivetech.com>; paul.walmsley@sifive.com; palmer@dabbelt.com; aou@eecs.berkeley.edu; >> conor@kernel.org; kernel@esmil.dk; robh+dt@kernel.org; emil.renner.berthing@canonical.com >> Cc: linux-riscv@lists.infradead.org; linux-kernel@vger.kernel.org; Leyfoon Tan <leyfoon.tan@starfivetech.com> >> Subject: Re: [PATCH 6/7] serial: xilinx_uartps: Add new compatible string for StarFive >> >> On 27/11/2023 02:36, Sia Jee Heng wrote: >>> This patch adds the new compatible string for StarFive JH8100 SoC >>> >>> Signed-off-by: Sia Jee Heng <jeeheng.sia@starfivetech.com> >>> Reviewed-by: Ley Foon Tan <leyfoon.tan@starfivetech.com> >>> --- >>> drivers/tty/serial/xilinx_uartps.c | 3 ++- >>> 1 file changed, 2 insertions(+), 1 deletion(-) >>> >>> diff --git a/drivers/tty/serial/xilinx_uartps.c b/drivers/tty/serial/xilinx_uartps.c >>> index 66a45a634158..170901c143c2 100644 >>> --- a/drivers/tty/serial/xilinx_uartps.c >>> +++ b/drivers/tty/serial/xilinx_uartps.c >>> @@ -1210,7 +1210,7 @@ OF_EARLYCON_DECLARE(cdns, "xlnx,xuartps", cdns_early_console_setup); >>> OF_EARLYCON_DECLARE(cdns, "cdns,uart-r1p8", cdns_early_console_setup); >>> OF_EARLYCON_DECLARE(cdns, "cdns,uart-r1p12", cdns_early_console_setup); >>> OF_EARLYCON_DECLARE(cdns, "xlnx,zynqmp-uart", cdns_early_console_setup); >>> - >>> +OF_EARLYCON_DECLARE(cdns, "starfive,jh8100-uart", cdns_early_console_setup); >>> >>> /* Static pointer to console port */ >>> static struct uart_port *console_port; >>> @@ -1448,6 +1448,7 @@ static const struct of_device_id cdns_uart_of_match[] = { >>> { .compatible = "cdns,uart-r1p8", }, >>> { .compatible = "cdns,uart-r1p12", .data = &zynqmp_uart_def }, >>> { .compatible = "xlnx,zynqmp-uart", .data = &zynqmp_uart_def }, >>> + { .compatible = "starfive,jh8100-uart", }, >> >> Why you do not express compatibility in your bindings? Skip this driver >> change. > The compatibility string was added to the binding in the 5th patch. We need to add this compatibility string to the driver, as the other compatibilities were used for other SoCs. You did not add "compatibility string" but compatible. I am asking why you are not expressing in your bindings the compatibility between this and other devices. And no, you do not need driver change for compatible devices, so again: skip this driver change. Best regards, Krzysztof _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply [flat|nested] 24+ messages in thread
* RE: [PATCH 6/7] serial: xilinx_uartps: Add new compatible string for StarFive 2023-11-28 7:21 ` Krzysztof Kozlowski @ 2023-11-28 7:57 ` JeeHeng Sia 0 siblings, 0 replies; 24+ messages in thread From: JeeHeng Sia @ 2023-11-28 7:57 UTC (permalink / raw) To: Krzysztof Kozlowski, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, conor@kernel.org, kernel@esmil.dk, robh+dt@kernel.org, emil.renner.berthing@canonical.com Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Leyfoon Tan > -----Original Message----- > From: Krzysztof Kozlowski <krzk@kernel.org> > Sent: Tuesday, November 28, 2023 3:21 PM > To: JeeHeng Sia <jeeheng.sia@starfivetech.com>; paul.walmsley@sifive.com; palmer@dabbelt.com; aou@eecs.berkeley.edu; > conor@kernel.org; kernel@esmil.dk; robh+dt@kernel.org; emil.renner.berthing@canonical.com > Cc: linux-riscv@lists.infradead.org; linux-kernel@vger.kernel.org; Leyfoon Tan <leyfoon.tan@starfivetech.com> > Subject: Re: [PATCH 6/7] serial: xilinx_uartps: Add new compatible string for StarFive > > On 28/11/2023 06:25, JeeHeng Sia wrote: > > > > > >> -----Original Message----- > >> From: Krzysztof Kozlowski <krzk@kernel.org> > >> Sent: Monday, November 27, 2023 4:49 PM > >> To: JeeHeng Sia <jeeheng.sia@starfivetech.com>; paul.walmsley@sifive.com; palmer@dabbelt.com; aou@eecs.berkeley.edu; > >> conor@kernel.org; kernel@esmil.dk; robh+dt@kernel.org; emil.renner.berthing@canonical.com > >> Cc: linux-riscv@lists.infradead.org; linux-kernel@vger.kernel.org; Leyfoon Tan <leyfoon.tan@starfivetech.com> > >> Subject: Re: [PATCH 6/7] serial: xilinx_uartps: Add new compatible string for StarFive > >> > >> On 27/11/2023 02:36, Sia Jee Heng wrote: > >>> This patch adds the new compatible string for StarFive JH8100 SoC > >>> > >>> Signed-off-by: Sia Jee Heng <jeeheng.sia@starfivetech.com> > >>> Reviewed-by: Ley Foon Tan <leyfoon.tan@starfivetech.com> > >>> --- > >>> drivers/tty/serial/xilinx_uartps.c | 3 ++- > >>> 1 file changed, 2 insertions(+), 1 deletion(-) > >>> > >>> diff --git a/drivers/tty/serial/xilinx_uartps.c b/drivers/tty/serial/xilinx_uartps.c > >>> index 66a45a634158..170901c143c2 100644 > >>> --- a/drivers/tty/serial/xilinx_uartps.c > >>> +++ b/drivers/tty/serial/xilinx_uartps.c > >>> @@ -1210,7 +1210,7 @@ OF_EARLYCON_DECLARE(cdns, "xlnx,xuartps", cdns_early_console_setup); > >>> OF_EARLYCON_DECLARE(cdns, "cdns,uart-r1p8", cdns_early_console_setup); > >>> OF_EARLYCON_DECLARE(cdns, "cdns,uart-r1p12", cdns_early_console_setup); > >>> OF_EARLYCON_DECLARE(cdns, "xlnx,zynqmp-uart", cdns_early_console_setup); > >>> - > >>> +OF_EARLYCON_DECLARE(cdns, "starfive,jh8100-uart", cdns_early_console_setup); > >>> > >>> /* Static pointer to console port */ > >>> static struct uart_port *console_port; > >>> @@ -1448,6 +1448,7 @@ static const struct of_device_id cdns_uart_of_match[] = { > >>> { .compatible = "cdns,uart-r1p8", }, > >>> { .compatible = "cdns,uart-r1p12", .data = &zynqmp_uart_def }, > >>> { .compatible = "xlnx,zynqmp-uart", .data = &zynqmp_uart_def }, > >>> + { .compatible = "starfive,jh8100-uart", }, > >> > >> Why you do not express compatibility in your bindings? Skip this driver > >> change. > > The compatibility string was added to the binding in the 5th patch. We need to add this compatibility string to the driver, as the > other compatibilities were used for other SoCs. > > You did not add "compatibility string" but compatible. I am asking why > you are not expressing in your bindings the compatibility between this > and other devices. > > And no, you do not need driver change for compatible devices, so again: > skip this driver change. Alright, I will skip this driver change. Thanks. > > > Best regards, > Krzysztof _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH 7/7] riscv: dts: starfive: Add initial StarFive JH8100 device tree 2023-11-27 1:35 [PATCH 0/7] Initial device tree support for StarFive JH8100 SoC Sia Jee Heng ` (5 preceding siblings ...) 2023-11-27 1:36 ` [PATCH 6/7] serial: xilinx_uartps: Add new compatible string for StarFive Sia Jee Heng @ 2023-11-27 1:36 ` Sia Jee Heng 2023-11-27 8:50 ` Krzysztof Kozlowski 6 siblings, 1 reply; 24+ messages in thread From: Sia Jee Heng @ 2023-11-27 1:36 UTC (permalink / raw) To: paul.walmsley, palmer, aou, conor, kernel, robh+dt, emil.renner.berthing Cc: linux-riscv, linux-kernel, jeeheng.sia, leyfoon.tan Add initial device tree for the StarFive JH8100 RISC-V SoC Signed-off-by: Sia Jee Heng <jeeheng.sia@starfivetech.com> Reviewed-by: Ley Foon Tan <leyfoon.tan@starfivetech.com> --- arch/riscv/boot/dts/starfive/Makefile | 1 + arch/riscv/boot/dts/starfive/jh8100-evb.dts | 42 +++ arch/riscv/boot/dts/starfive/jh8100.dtsi | 365 ++++++++++++++++++++ 3 files changed, 408 insertions(+) create mode 100644 arch/riscv/boot/dts/starfive/jh8100-evb.dts create mode 100644 arch/riscv/boot/dts/starfive/jh8100.dtsi diff --git a/arch/riscv/boot/dts/starfive/Makefile b/arch/riscv/boot/dts/starfive/Makefile index 0141504c0f5c..fbb0dc619102 100644 --- a/arch/riscv/boot/dts/starfive/Makefile +++ b/arch/riscv/boot/dts/starfive/Makefile @@ -10,3 +10,4 @@ dtb-$(CONFIG_ARCH_STARFIVE) += jh7100-starfive-visionfive-v1.dtb dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-v1.2a.dtb dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-v1.3b.dtb +dtb-$(CONFIG_ARCH_STARFIVE) += jh8100-evb.dtb diff --git a/arch/riscv/boot/dts/starfive/jh8100-evb.dts b/arch/riscv/boot/dts/starfive/jh8100-evb.dts new file mode 100644 index 000000000000..67c4964a8773 --- /dev/null +++ b/arch/riscv/boot/dts/starfive/jh8100-evb.dts @@ -0,0 +1,42 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (c) 2021-2023 StarFive Technology Co., Ltd. + */ + +#include "jh8100.dtsi" + +/ { + model = "StarFive JH8100 EVB"; + compatible = "starfive,jh8100-evb", "starfive,jh8100"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + cpus { + timebase-frequency = <4000000>; + + }; + + memory { + device_type = "memory"; + reg = <0x0 0x40000000 0x2 0x00000000>; /* 8GB */ + }; + + soc { + clk_uart: clk_uart { + compatible = "fixed-clock"; /* Initial clock handler for UART */ + #clock-cells = <0>; + clock-frequency = <24000000>; + }; + }; +}; + +&uart0 { + status = "okay"; + clocks = <&clk_uart>, <&clk_uart>; +}; diff --git a/arch/riscv/boot/dts/starfive/jh8100.dtsi b/arch/riscv/boot/dts/starfive/jh8100.dtsi new file mode 100644 index 000000000000..1b338d4cb985 --- /dev/null +++ b/arch/riscv/boot/dts/starfive/jh8100.dtsi @@ -0,0 +1,365 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (c) 2021-2023 StarFive Technology Co., Ltd. + */ + +/dts-v1/; + +/ { + compatible = "starfive,jh8100"; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "starfive,dubhe-80", "riscv"; + capacity-dmips-mhz = <768>; + d-cache-block-size = <64>; + d-cache-sets = <512>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <48>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <512>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <48>; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2c0>; + reg = <0x0>; + riscv,isa = "rv64imafdch"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "h", "zicntr", + "zicsr", "zifencei", "zihintpause", "zihpm", + "zba", "zbb", "zbs", "sscofpmf"; + tlb-split; + + cpu0_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + cpu1: cpu@1 { + compatible = "starfive,dubhe-80", "riscv"; + capacity-dmips-mhz = <768>; + d-cache-block-size = <64>; + d-cache-sets = <512>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <48>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <512>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <48>; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2c1>; + reg = <0x1>; + riscv,isa = "rv64imafdch"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "h", "zicntr", + "zicsr", "zifencei", "zihintpause", "zihpm", + "zba", "zbb", "zbs", "sscofpmf"; + tlb-split; + + cpu1_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + cpu2: cpu@2 { + compatible = "starfive,dubhe-90", "riscv"; + capacity-dmips-mhz = <1024>; + d-cache-block-size = <64>; + d-cache-sets = <1024>; + d-cache-size = <65536>; + d-tlb-sets = <1>; + d-tlb-size = <48>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <1024>; + i-cache-size = <65536>; + i-tlb-sets = <1>; + i-tlb-size = <48>; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2c2>; + reg = <0x2>; + riscv,isa = "rv64imafdch"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "h", "zicntr", + "zicsr", "zifencei", "zihintpause", "zihpm", + "zba", "zbb", "zbs", "sscofpmf"; + tlb-split; + + cpu2_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + cpu3: cpu@3 { + compatible = "starfive,dubhe-90", "riscv"; + capacity-dmips-mhz = <1024>; + d-cache-block-size = <64>; + d-cache-sets = <1024>; + d-cache-size = <65536>; + d-tlb-sets = <1>; + d-tlb-size = <48>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <1024>; + i-cache-size = <65536>; + i-tlb-sets = <1>; + i-tlb-size = <48>; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2c2>; + reg = <0x3>; + riscv,isa = "rv64imafdch"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "h", "zicntr", + "zicsr", "zifencei", "zihintpause", "zihpm", + "zba", "zbb", "zbs", "sscofpmf"; + tlb-split; + + cpu3_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + cpu4: cpu@4 { + compatible = "starfive,dubhe-90", "riscv"; + capacity-dmips-mhz = <1024>; + d-cache-block-size = <64>; + d-cache-sets = <1024>; + d-cache-size = <65536>; + d-tlb-sets = <1>; + d-tlb-size = <48>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <1024>; + i-cache-size = <65536>; + i-tlb-sets = <1>; + i-tlb-size = <48>; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2c2>; + reg = <0x4>; + riscv,isa = "rv64imafdch"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "h", "zicntr", + "zicsr", "zifencei", "zihintpause", "zihpm", + "zba", "zbb", "zbs", "sscofpmf"; + tlb-split; + + cpu4_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + cpu5: cpu@5 { + compatible = "starfive,dubhe-90", "riscv"; + capacity-dmips-mhz = <1024>; + d-cache-block-size = <64>; + d-cache-sets = <1024>; + d-cache-size = <65536>; + d-tlb-sets = <1>; + d-tlb-size = <48>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <1024>; + i-cache-size = <65536>; + i-tlb-sets = <1>; + i-tlb-size = <48>; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2c2>; + reg = <0x5>; + riscv,isa = "rv64imafdch"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "h", "zicntr", + "zicsr", "zifencei", "zihintpause", "zihpm", + "zba", "zbb", "zbs", "sscofpmf"; + tlb-split; + + cpu5_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + }; + + cluster1 { + core0 { + cpu = <&cpu1>; + }; + }; + + cluster2 { + core0 { + cpu = <&cpu2>; + }; + + core1 { + cpu = <&cpu3>; + }; + + core2 { + cpu = <&cpu4>; + }; + + core3 { + cpu = <&cpu5>; + }; + }; + }; + + l2c0: cache-controller-0 { + compatible = "cache"; + cache-block-size = <64>; + cache-level = <2>; + cache-sets = <512>; + cache-size = <0x40000>; + cache-unified; + next-level-cache = <&l3_cache>; + }; + + l2c1: cache-controller-1 { + compatible = "cache"; + cache-block-size = <64>; + cache-level = <2>; + cache-sets = <512>; + cache-size = <0x40000>; + cache-unified; + next-level-cache = <&l3_cache>; + }; + + l2c2: cache-controller-2{ + compatible = "cache"; + cache-block-size = <64>; + cache-level = <2>; + cache-sets = <4096>; + cache-size = <0x200000>; + cache-unified; + next-level-cache = <&l3_cache>; + }; + + l3_cache: cache-controller-3 { + compatible = "cache"; + cache-block-size = <64>; + cache-level = <3>; + cache-sets = <8192>; + cache-size = <0x400000>; + cache-unified; + }; + }; + + soc { + compatible = "simple-bus"; + interrupt-parent = <&plic>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + clint: clint@2000000 { + compatible = "starfive,jh8100-clint", "sifive,clint0"; + reg = <0x0 0x2000000 0x0 0x10000>; + interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>, + <&cpu1_intc 3>, <&cpu1_intc 7>, + <&cpu2_intc 3>, <&cpu2_intc 7>, + <&cpu3_intc 3>, <&cpu3_intc 7>, + <&cpu4_intc 3>, <&cpu4_intc 7>, + <&cpu5_intc 3>, <&cpu5_intc 7>; + }; + + plic: interrupt-controller@c000000 { + #interrupt-cells = <1>; + #address-cells = <0>; + compatible = "starfive,jh8100-plic", "sifive,plic-1.0.0"; + reg = <0x0 0x0c000000 0x0 0x4000000>; + riscv,ndev = <200>; + interrupt-controller; + interrupts-extended = <&cpu0_intc 11>, <&cpu1_intc 11>, + <&cpu0_intc 9>, <&cpu1_intc 9>, + <&cpu2_intc 11>, <&cpu3_intc 11>, + <&cpu4_intc 11>, <&cpu5_intc 11>, + <&cpu2_intc 9>, <&cpu3_intc 9>, + <&cpu4_intc 9>, <&cpu5_intc 9>; + }; + + uart0: serial@12160000 { + compatible = "starfive,jh8100-uart"; + reg = <0x0 0x12160000 0x0 0x10000>; + clock-names = "uart_clk", "pclk"; + interrupts = <67>; + status = "disabled"; + }; + + uart1: serial@12170000 { + compatible = "starfive,jh8100-uart"; + reg = <0x0 0x12170000 0x0 0x10000>; + clock-names = "uart_clk", "pclk"; + interrupts = <68>; + status = "disabled"; + }; + + uart2: serial@12180000 { + compatible = "starfive,jh8100-uart"; + reg = <0x0 0x12180000 0x0 0x10000>; + clock-names = "uart_clk", "pclk"; + interrupts = <69>; + status = "disabled"; + }; + + uart3: serial@12190000 { + compatible = "starfive,jh8100-uart"; + reg = <0x0 0x12190000 0x0 0x10000>; + clock-names = "uart_clk", "pclk"; + interrupts = <70>; + status = "disabled"; + }; + + uart4: serial@121a0000 { + compatible = "starfive,jh8100-uart"; + reg = <0x0 0x121a0000 0x0 0x10000>; + clock-names = "uart_clk", "pclk"; + interrupts = <71>; + status = "disabled"; + }; + + uart5: serial@127d0000 { + compatible = "starfive,jh8100-uart"; + reg = <0x0 0x127d0000 0x0 0x10000>; + clock-names = "uart_clk", "pclk"; + interrupts = <72>; + status = "disabled"; + }; + + uart6: serial@127e0000 { + compatible = "starfive,jh8100-uart"; + reg = <0x0 0x127e0000 0x0 0x10000>; + clock-names = "uart_clk", "pclk"; + interrupts = <73>; + status = "disabled"; + }; + + }; +}; -- 2.34.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply related [flat|nested] 24+ messages in thread
* Re: [PATCH 7/7] riscv: dts: starfive: Add initial StarFive JH8100 device tree 2023-11-27 1:36 ` [PATCH 7/7] riscv: dts: starfive: Add initial StarFive JH8100 device tree Sia Jee Heng @ 2023-11-27 8:50 ` Krzysztof Kozlowski 2023-11-27 9:20 ` Conor Dooley 2023-11-28 3:23 ` JeeHeng Sia 0 siblings, 2 replies; 24+ messages in thread From: Krzysztof Kozlowski @ 2023-11-27 8:50 UTC (permalink / raw) To: Sia Jee Heng, paul.walmsley, palmer, aou, conor, kernel, robh+dt, emil.renner.berthing Cc: linux-riscv, linux-kernel, leyfoon.tan On 27/11/2023 02:36, Sia Jee Heng wrote: > Add initial device tree for the StarFive JH8100 RISC-V SoC > > Signed-off-by: Sia Jee Heng <jeeheng.sia@starfivetech.com> > Reviewed-by: Ley Foon Tan <leyfoon.tan@starfivetech.com> > --- > arch/riscv/boot/dts/starfive/Makefile | 1 + > arch/riscv/boot/dts/starfive/jh8100-evb.dts | 42 +++ > arch/riscv/boot/dts/starfive/jh8100.dtsi | 365 ++++++++++++++++++++ > 3 files changed, 408 insertions(+) > create mode 100644 arch/riscv/boot/dts/starfive/jh8100-evb.dts > create mode 100644 arch/riscv/boot/dts/starfive/jh8100.dtsi > > diff --git a/arch/riscv/boot/dts/starfive/Makefile b/arch/riscv/boot/dts/starfive/Makefile > index 0141504c0f5c..fbb0dc619102 100644 > --- a/arch/riscv/boot/dts/starfive/Makefile > +++ b/arch/riscv/boot/dts/starfive/Makefile > @@ -10,3 +10,4 @@ dtb-$(CONFIG_ARCH_STARFIVE) += jh7100-starfive-visionfive-v1.dtb > > dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-v1.2a.dtb > dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-v1.3b.dtb > +dtb-$(CONFIG_ARCH_STARFIVE) += jh8100-evb.dtb > diff --git a/arch/riscv/boot/dts/starfive/jh8100-evb.dts b/arch/riscv/boot/dts/starfive/jh8100-evb.dts > new file mode 100644 > index 000000000000..67c4964a8773 > --- /dev/null > +++ b/arch/riscv/boot/dts/starfive/jh8100-evb.dts > @@ -0,0 +1,42 @@ > +// SPDX-License-Identifier: GPL-2.0 OR MIT > +/* > + * Copyright (c) 2021-2023 StarFive Technology Co., Ltd. > + */ > + > +#include "jh8100.dtsi" > + > +/ { > + model = "StarFive JH8100 EVB"; > + compatible = "starfive,jh8100-evb", "starfive,jh8100"; > + > + aliases { > + serial0 = &uart0; > + }; > + > + chosen { > + stdout-path = "serial0:115200n8"; > + }; > + > + cpus { > + timebase-frequency = <4000000>; This was fixed recently on the mailing lists. > + > + }; > + > + memory { > + device_type = "memory"; > + reg = <0x0 0x40000000 0x2 0x00000000>; /* 8GB */ > + }; > + > + soc { > + clk_uart: clk_uart { Undercores are not allowed in node names. Use hyphen. Also, boards must not add nodes to the soc. This is board, not SoC DTS. ... > + > + uart6: serial@127e0000 { > + compatible = "starfive,jh8100-uart"; > + reg = <0x0 0x127e0000 0x0 0x10000>; > + clock-names = "uart_clk", "pclk"; > + interrupts = <73>; > + status = "disabled"; > + }; > + Stray blank line. In other places as well. > + }; > +}; Best regards, Krzysztof _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH 7/7] riscv: dts: starfive: Add initial StarFive JH8100 device tree 2023-11-27 8:50 ` Krzysztof Kozlowski @ 2023-11-27 9:20 ` Conor Dooley 2023-11-27 9:29 ` Krzysztof Kozlowski 2023-11-28 3:23 ` JeeHeng Sia 1 sibling, 1 reply; 24+ messages in thread From: Conor Dooley @ 2023-11-27 9:20 UTC (permalink / raw) To: Krzysztof Kozlowski Cc: Sia Jee Heng, paul.walmsley, palmer, aou, conor, kernel, robh+dt, emil.renner.berthing, linux-riscv, linux-kernel, leyfoon.tan [-- Attachment #1.1: Type: text/plain, Size: 887 bytes --] On Mon, Nov 27, 2023 at 09:50:35AM +0100, Krzysztof Kozlowski wrote: > On 27/11/2023 02:36, Sia Jee Heng wrote: > > + chosen { > > + stdout-path = "serial0:115200n8"; > > + }; > > + > > + cpus { > > + timebase-frequency = <4000000>; > > This was fixed recently on the mailing lists. Actually, I only fixed this for the microchip stuff, as I don't know whether or not having this in $board.dts is valid for other cases. As far as I understand it, this works just like regular clock nodes, so if the clock is provided by an off-chip crystal it is okay to have it in $board.dts, but otherwise it should go in $soc.dts. The same applies to the jh7100/jh7110, so if you could clarify it for that platform too, that'd be great. Doing it in response to https://lore.kernel.org/all/20231126-attractor-swampland-b1b95bd1322b@spud/ would be great. Thanks, Conor. [-- Attachment #1.2: signature.asc --] [-- Type: application/pgp-signature, Size: 228 bytes --] [-- Attachment #2: Type: text/plain, Size: 161 bytes --] _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH 7/7] riscv: dts: starfive: Add initial StarFive JH8100 device tree 2023-11-27 9:20 ` Conor Dooley @ 2023-11-27 9:29 ` Krzysztof Kozlowski 0 siblings, 0 replies; 24+ messages in thread From: Krzysztof Kozlowski @ 2023-11-27 9:29 UTC (permalink / raw) To: Conor Dooley Cc: Sia Jee Heng, paul.walmsley, palmer, aou, conor, kernel, robh+dt, emil.renner.berthing, linux-riscv, linux-kernel, leyfoon.tan On 27/11/2023 10:20, Conor Dooley wrote: > On Mon, Nov 27, 2023 at 09:50:35AM +0100, Krzysztof Kozlowski wrote: >> On 27/11/2023 02:36, Sia Jee Heng wrote: > >>> + chosen { >>> + stdout-path = "serial0:115200n8"; >>> + }; >>> + >>> + cpus { >>> + timebase-frequency = <4000000>; >> >> This was fixed recently on the mailing lists. > > Actually, I only fixed this for the microchip stuff, as I don't know > whether or not having this in $board.dts is valid for other cases. > > As far as I understand it, this works just like regular clock nodes, so > if the clock is provided by an off-chip crystal it is okay to have it in > $board.dts, but otherwise it should go in $soc.dts. > > The same applies to the jh7100/jh7110, so if you could clarify it for > that platform too, that'd be great. Doing it in response to > https://lore.kernel.org/all/20231126-attractor-swampland-b1b95bd1322b@spud/ > would be great. OK, then it should be added via label syntax, not by full node path. Best regards, Krzysztof _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply [flat|nested] 24+ messages in thread
* RE: [PATCH 7/7] riscv: dts: starfive: Add initial StarFive JH8100 device tree 2023-11-27 8:50 ` Krzysztof Kozlowski 2023-11-27 9:20 ` Conor Dooley @ 2023-11-28 3:23 ` JeeHeng Sia 1 sibling, 0 replies; 24+ messages in thread From: JeeHeng Sia @ 2023-11-28 3:23 UTC (permalink / raw) To: Krzysztof Kozlowski, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, conor@kernel.org, kernel@esmil.dk, robh+dt@kernel.org, emil.renner.berthing@canonical.com Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Leyfoon Tan > -----Original Message----- > From: Krzysztof Kozlowski <krzk@kernel.org> > Sent: Monday, November 27, 2023 4:51 PM > To: JeeHeng Sia <jeeheng.sia@starfivetech.com>; paul.walmsley@sifive.com; palmer@dabbelt.com; aou@eecs.berkeley.edu; > conor@kernel.org; kernel@esmil.dk; robh+dt@kernel.org; emil.renner.berthing@canonical.com > Cc: linux-riscv@lists.infradead.org; linux-kernel@vger.kernel.org; Leyfoon Tan <leyfoon.tan@starfivetech.com> > Subject: Re: [PATCH 7/7] riscv: dts: starfive: Add initial StarFive JH8100 device tree > > On 27/11/2023 02:36, Sia Jee Heng wrote: > > Add initial device tree for the StarFive JH8100 RISC-V SoC > > > > Signed-off-by: Sia Jee Heng <jeeheng.sia@starfivetech.com> > > Reviewed-by: Ley Foon Tan <leyfoon.tan@starfivetech.com> > > --- > > arch/riscv/boot/dts/starfive/Makefile | 1 + > > arch/riscv/boot/dts/starfive/jh8100-evb.dts | 42 +++ > > arch/riscv/boot/dts/starfive/jh8100.dtsi | 365 ++++++++++++++++++++ > > 3 files changed, 408 insertions(+) > > create mode 100644 arch/riscv/boot/dts/starfive/jh8100-evb.dts > > create mode 100644 arch/riscv/boot/dts/starfive/jh8100.dtsi > > > > diff --git a/arch/riscv/boot/dts/starfive/Makefile b/arch/riscv/boot/dts/starfive/Makefile > > index 0141504c0f5c..fbb0dc619102 100644 > > --- a/arch/riscv/boot/dts/starfive/Makefile > > +++ b/arch/riscv/boot/dts/starfive/Makefile > > @@ -10,3 +10,4 @@ dtb-$(CONFIG_ARCH_STARFIVE) += jh7100-starfive-visionfive-v1.dtb > > > > dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-v1.2a.dtb > > dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-v1.3b.dtb > > +dtb-$(CONFIG_ARCH_STARFIVE) += jh8100-evb.dtb > > diff --git a/arch/riscv/boot/dts/starfive/jh8100-evb.dts b/arch/riscv/boot/dts/starfive/jh8100-evb.dts > > new file mode 100644 > > index 000000000000..67c4964a8773 > > --- /dev/null > > +++ b/arch/riscv/boot/dts/starfive/jh8100-evb.dts > > @@ -0,0 +1,42 @@ > > +// SPDX-License-Identifier: GPL-2.0 OR MIT > > +/* > > + * Copyright (c) 2021-2023 StarFive Technology Co., Ltd. > > + */ > > + > > +#include "jh8100.dtsi" > > + > > +/ { > > + model = "StarFive JH8100 EVB"; > > + compatible = "starfive,jh8100-evb", "starfive,jh8100"; > > + > > + aliases { > > + serial0 = &uart0; > > + }; > > + > > + chosen { > > + stdout-path = "serial0:115200n8"; > > + }; > > + > > + cpus { > > + timebase-frequency = <4000000>; > > This was fixed recently on the mailing lists. The timebase-frequency on StarFive JH8100 SoC is set by an internal clk divider, will move the property to jh8100.dtsi. Thanks. > > > > + > > + }; > > + > > + memory { > > + device_type = "memory"; > > + reg = <0x0 0x40000000 0x2 0x00000000>; /* 8GB */ > > + }; > > + > > + soc { > > + clk_uart: clk_uart { > > Undercores are not allowed in node names. Use hyphen. Noted. > > Also, boards must not add nodes to the soc. This is board, not SoC DTS. Noted. Will move it to dtsi. > > ... > > > + > > + uart6: serial@127e0000 { > > + compatible = "starfive,jh8100-uart"; > > + reg = <0x0 0x127e0000 0x0 0x10000>; > > + clock-names = "uart_clk", "pclk"; > > + interrupts = <73>; > > + status = "disabled"; > > + }; > > + > > Stray blank line. In other places as well. Noted. > > > + }; > > +}; > > Best regards, > Krzysztof _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply [flat|nested] 24+ messages in thread
end of thread, other threads:[~2023-11-28 7:58 UTC | newest] Thread overview: 24+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2023-11-27 1:35 [PATCH 0/7] Initial device tree support for StarFive JH8100 SoC Sia Jee Heng 2023-11-27 1:35 ` [PATCH 1/7] dt-bindings: riscv: Add StarFive Dubhe compatibles Sia Jee Heng 2023-11-27 8:47 ` Krzysztof Kozlowski 2023-11-27 1:35 ` [PATCH 2/7] dt-bindings: riscv: Add StarFive JH8100 SoC Sia Jee Heng 2023-11-27 1:35 ` [PATCH 3/7] dt-bindings: timer: Add StarFive JH8100 clint Sia Jee Heng 2023-11-27 8:47 ` Krzysztof Kozlowski 2023-11-28 5:24 ` JeeHeng Sia 2023-11-28 7:19 ` Krzysztof Kozlowski 2023-11-28 7:56 ` JeeHeng Sia 2023-11-27 1:35 ` [PATCH 4/7] dt-bindings: interrupt-controller: Add StarFive JH8100 plic Sia Jee Heng 2023-11-27 8:48 ` Krzysztof Kozlowski 2023-11-27 1:36 ` [PATCH 5/7] dt-bindings: xilinx: Add StarFive compatible string Sia Jee Heng 2023-11-27 8:48 ` Krzysztof Kozlowski 2023-11-28 5:24 ` JeeHeng Sia 2023-11-27 1:36 ` [PATCH 6/7] serial: xilinx_uartps: Add new compatible string for StarFive Sia Jee Heng 2023-11-27 8:49 ` Krzysztof Kozlowski 2023-11-28 5:25 ` JeeHeng Sia 2023-11-28 7:21 ` Krzysztof Kozlowski 2023-11-28 7:57 ` JeeHeng Sia 2023-11-27 1:36 ` [PATCH 7/7] riscv: dts: starfive: Add initial StarFive JH8100 device tree Sia Jee Heng 2023-11-27 8:50 ` Krzysztof Kozlowski 2023-11-27 9:20 ` Conor Dooley 2023-11-27 9:29 ` Krzysztof Kozlowski 2023-11-28 3:23 ` JeeHeng Sia
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