[PATCH 0/3] Add USB support for Sophgo CV1800/SG200x SoCs

[PATCH 0/3] Add USB support for Sophgo CV1800/SG200x SoCs

[Yao Zi]

Sophgo CV1800/SG200x SoCs integrate a USB 2.0 phy and a USB 2.0
controller based on dwc2 IP. This series implements a basic driver
for the USB phy and add USB-related device tree nodes.

Yao Zi (3):
  dt-bindings: phy: add YAML schema for cv1800-usb-phy driver bindings
  riscv: dts: sophgo: add nodes for USB phy and controller
  phy: sophgo: add usb phy driver for Sophgo CV1800 SoCs

 .../bindings/phy/sophgo,cv1800-usb-phy.yaml   |  67 ++++++
 arch/riscv/boot/dts/sophgo/cv18xx.dtsi        |  23 ++
 drivers/phy/Kconfig                           |   1 +
 drivers/phy/Makefile                          |   1 +
 drivers/phy/sophgo/Kconfig                    |  10 +
 drivers/phy/sophgo/Makefile                   |   2 +
 drivers/phy/sophgo/phy-cv1800-usb.c           | 213 ++++++++++++++++++
 7 files changed, 317 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/sophgo,cv1800-usb-phy.yaml
 create mode 100644 drivers/phy/sophgo/Kconfig
 create mode 100644 drivers/phy/sophgo/Makefile
 create mode 100644 drivers/phy/sophgo/phy-cv1800-usb.c

-- 
2.45.2


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[PATCH 1/3] dt-bindings: phy: add YAML schema for cv1800-usb-phy driver bindings

[Yao Zi]

cv1800-usb-phy driver supports USB 2.0 phys integrated in Sophgo
Cv1800/SG200x SoCs. Add YAML schema for its binding.

Signed-off-by: Yao Zi <ziyao@disroot.org>
---
 .../bindings/phy/sophgo,cv1800-usb-phy.yaml   | 67 +++++++++++++++++++
 1 file changed, 67 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/sophgo,cv1800-usb-phy.yaml

diff --git a/Documentation/devicetree/bindings/phy/sophgo,cv1800-usb-phy.yaml b/Documentation/devicetree/bindings/phy/sophgo,cv1800-usb-phy.yaml
new file mode 100644
index 000000000000..0403d899e23b
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/sophgo,cv1800-usb-phy.yaml
@@ -0,0 +1,67 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+# Copyright 2019 BayLibre, SAS
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/sophgo,cv1800-usb-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Sophgo CV1800 USB PHY
+
+maintainers:
+  - Yao Zi <ziyao@disroot.org>
+
+properties:
+  compatible:
+    enum:
+      - sophgo,cv1800-usb-phy
+
+  reg:
+    maxItems: 2
+
+  reg-names:
+    items:
+      - const: phy
+      - const: pin
+
+  clocks:
+    maxItems: 4
+
+  clock-names:
+    items:
+      - const: apb
+      - const: 125m
+      - const: 33k
+      - const: 12m
+
+  "#phy-cells":
+    const: 0
+
+  dr_role:
+    enum:
+      - host
+      - device
+
+required:
+  - compatible
+  - reg
+  - reg-names
+  - clocks
+  - clock-names
+  - "#phy-cells"
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/sophgo,cv1800.h>
+    usb_phy: usb-phy@3006000 {
+        compatible = "sophgo,cv1800-usb-phy";
+        reg = <0x300600 0x60>, <0x3000048 0x4>;
+        reg-names = "phy", "pin";
+        clocks = <&clk CLK_APB_USB>,
+                 <&clk CLK_USB_125M>,
+                 <&clk CLK_USB_33K>,
+                 <&clk CLK_USB_12M>;
+        clock-names = "apb", "125m", "33k", "12m";
+        #phy-cells = <0>;
+    };
-- 
2.45.2


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[PATCH 2/3] riscv: dts: sophgo: add nodes for USB phy and controller

[Yao Zi]

CV1800/SG200x SoCs integrate a USB 2.0 phy and a USB controller based
on dwc2 IP. Add device tree nodes for these peripherals.

Signed-off-by: Yao Zi <ziyao@disroot.org>
---
 arch/riscv/boot/dts/sophgo/cv18xx.dtsi | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)

diff --git a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
index 891932ae470f..06461f1f1986 100644
--- a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
+++ b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
@@ -61,6 +61,18 @@ clk: clock-controller@3002000 {
 			#clock-cells = <1>;
 		};
 
+		usb_phy: usb-phy@3006000 {
+			compatible = "sophgo,cv1800-usb-phy";
+			reg = <0x3006000 0x60>, <0x3000048 0x4>;
+			reg-names = "phy", "pin";
+			clocks = <&clk CLK_APB_USB>,
+				 <&clk CLK_USB_125M>,
+				 <&clk CLK_USB_33K>,
+				 <&clk CLK_USB_12M>;
+			clock-names = "apb", "125m", "33k", "12m";
+			#phy-cells = <0>;
+		};
+
 		gpio0: gpio@3020000 {
 			compatible = "snps,dw-apb-gpio";
 			reg = <0x3020000 0x1000>;
@@ -297,6 +309,17 @@ sdhci0: mmc@4310000 {
 			status = "disabled";
 		};
 
+		usb_otg: usb@4340000 {
+			compatible = "sophgo,cv1800-usb";
+			reg = <0x4340000 0x10000>;
+			clocks = <&clk CLK_AXI4_USB>;
+			clock-names = "otg";
+			dr_mode = "otg";
+			interrupts = <30 IRQ_TYPE_LEVEL_HIGH>;
+			phys = <&usb_phy>;
+			phy-names = "usb2-phy";
+		};
+
 		plic: interrupt-controller@70000000 {
 			reg = <0x70000000 0x4000000>;
 			interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;
-- 
2.45.2


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[PATCH 3/3] phy: sophgo: add usb phy driver for Sophgo CV1800 SoCs

[Yao Zi]

This adds a new driver for USB2 phys integrated in Sophgo CV1800 and
SG200x SoCs, which have the same design.

Most CV1800/SG200x boards have broken VBUS/ID detection, so we force
ID status to be specified in the device tree. This phy also supports
charger detection, which could be implemented later.

Unfortunately, there is no description about the phy in the public
datasheet. The driver was written by reading Sophgo GPL kernel source
and dumping registers on actual SG2002 devices.

Signed-off-by: Yao Zi <ziyao@disroot.org>
---
 drivers/phy/Kconfig                 |   1 +
 drivers/phy/Makefile                |   1 +
 drivers/phy/sophgo/Kconfig          |  10 ++
 drivers/phy/sophgo/Makefile         |   2 +
 drivers/phy/sophgo/phy-cv1800-usb.c | 213 ++++++++++++++++++++++++++++
 5 files changed, 227 insertions(+)
 create mode 100644 drivers/phy/sophgo/Kconfig
 create mode 100644 drivers/phy/sophgo/Makefile
 create mode 100644 drivers/phy/sophgo/phy-cv1800-usb.c

diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 787354b849c7..596b37ab3191 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -92,6 +92,7 @@ source "drivers/phy/renesas/Kconfig"
 source "drivers/phy/rockchip/Kconfig"
 source "drivers/phy/samsung/Kconfig"
 source "drivers/phy/socionext/Kconfig"
+source "drivers/phy/sophgo/Kconfig"
 source "drivers/phy/st/Kconfig"
 source "drivers/phy/starfive/Kconfig"
 source "drivers/phy/sunplus/Kconfig"
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index 868a220ed0f6..7ff32f0ae08a 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -31,6 +31,7 @@ obj-y					+= allwinner/	\
 					   rockchip/	\
 					   samsung/	\
 					   socionext/	\
+					   sophgo/	\
 					   st/		\
 					   starfive/	\
 					   sunplus/	\
diff --git a/drivers/phy/sophgo/Kconfig b/drivers/phy/sophgo/Kconfig
new file mode 100644
index 000000000000..6feb5795f1fc
--- /dev/null
+++ b/drivers/phy/sophgo/Kconfig
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+config PHY_SOPHGO_CV1800_USB
+	tristate "SOPHGO CV1800 USB 2.0 PHY driver"
+	depends on OF && (ARCH_SOPHGO || COMPILE_TEST)
+	select GENERIC_PHY
+	help
+	  Enable this to support the USB 2.0 PHY on Sophgo CV1800
+	  and SG200x SoCs.
+	  If unsure, say N.
diff --git a/drivers/phy/sophgo/Makefile b/drivers/phy/sophgo/Makefile
new file mode 100644
index 000000000000..b4b9de0697e7
--- /dev/null
+++ b/drivers/phy/sophgo/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0-only
+obj-$(CONFIG_PHY_SOPHGO_CV1800_USB)	+= phy-cv1800-usb.o
diff --git a/drivers/phy/sophgo/phy-cv1800-usb.c b/drivers/phy/sophgo/phy-cv1800-usb.c
new file mode 100644
index 000000000000..873c72bd95cf
--- /dev/null
+++ b/drivers/phy/sophgo/phy-cv1800-usb.c
@@ -0,0 +1,213 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * USB PHY driver for Sophgo CV1800 SoCs.
+ *
+ * Copyright 2024 Yao Zi <ziyao@disroot.org>
+ */
+
+#include <linux/clk.h>
+#include <linux/device.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/phy/phy.h>
+
+#define CV1800_REG04				0x04
+#define CV1800_REG14				0x14
+#define  CV1800_REG14_UTMI_OVERRIDE		BIT(0)
+#define  CV1800_REG14_OPMODE_MASK		(0x3 << 1)
+#define  CV1800_REG14_OPMODE_SHIFT		1
+#define  CV1800_REG14_XCVRSEL_MASK		(0x3 << 3)
+#define  CV1800_REG14_XCVRSEL_SHIFT		3
+#define  CV1800_REG14_TERMSEL			BIT(5)
+#define  CV1800_REG14_DPPULLDOWN		BIT(6)
+#define  CV1800_REG14_DMPULLDOWN		BIT(7)
+#define  CV1800_REG14_UTMI_RESET		BIT(8)
+#define CV1800_REG20				0x20
+#define  CV1800_REG20_BC_EN			BIT(0)
+#define  CV1800_REG20_DCD_EN			BIT(1)
+#define  CV1800_REG20_DP_CMP_EN			BIT(2)
+#define  CV1800_REG20_DM_CMP_EN			BIT(3)
+#define  CV1800_REG20_VDP_SRC_EN		BIT(4)
+#define  CV1800_REG20_VDM_SRC_EN		BIT(5)
+#define  CV1800_REG20_CHG_DET			BIT(16)
+#define  CV1800_REG20_DP_DET			BIT(17)
+
+#define CV1800_PIN_ID_OVERWRITE_EN		BIT(6)
+#define CV1800_PIN_ID_OVERWRITE_VALUE(v)	((v) << 7)
+
+enum cv1800_usb_phy_role {
+	CV1800_USB_PHY_HOST	= 0,
+	CV1800_USB_PHY_DEVICE	= 1,
+};
+
+struct cv1800_usb_phy_priv {
+	void __iomem *regs;
+	void __iomem *pinreg;
+	struct clk *clk_apb;
+	struct clk *clk_125m;
+	struct clk *clk_33k;
+	struct clk *clk_12m;
+	enum cv1800_usb_phy_role role;
+};
+
+static void
+cv1800_usb_phy_set_role(struct cv1800_usb_phy_priv *priv,
+			enum cv1800_usb_phy_role role)
+{
+	writel(CV1800_PIN_ID_OVERWRITE_EN | CV1800_PIN_ID_OVERWRITE_VALUE(role),
+	       priv->pinreg);
+}
+
+static int cv1800_usb_phy_init(struct phy *phy)
+{
+	struct cv1800_usb_phy_priv *priv = phy_get_drvdata(phy);
+	int ret = 0;
+
+	ret = clk_prepare_enable(priv->clk_apb);
+	if (ret)
+		return ret;
+
+	ret = clk_prepare_enable(priv->clk_125m);
+	if (ret)
+		goto err_clk_125m;
+
+	ret = clk_prepare_enable(priv->clk_33k);
+	if (ret)
+		goto err_clk_33k;
+
+	ret = clk_prepare_enable(priv->clk_12m);
+	if (ret)
+		goto err_clk_12m;
+
+	writel(0xa, priv->regs + CV1800_REG04);		/* magic number	*/
+	writel(0, priv->regs + CV1800_REG14);
+	writel(0, priv->regs + CV1800_REG20);
+
+	cv1800_usb_phy_set_role(priv, priv->role);
+
+	return 0;
+
+err_clk_12m:
+	clk_disable_unprepare(priv->clk_33k);
+err_clk_33k:
+	clk_disable_unprepare(priv->clk_125m);
+err_clk_125m:
+	clk_disable_unprepare(priv->clk_apb);
+
+	return ret;
+}
+
+static int cv1800_usb_phy_exit(struct phy *phy)
+{
+	struct cv1800_usb_phy_priv *priv = phy_get_drvdata(phy);
+
+	clk_disable_unprepare(priv->clk_33k);
+	clk_disable_unprepare(priv->clk_125m);
+	clk_disable_unprepare(priv->clk_apb);
+
+	return 0;
+}
+
+static const struct phy_ops cv1800_usb_phy_ops = {
+	.init = cv1800_usb_phy_init,
+	.exit = cv1800_usb_phy_exit,
+};
+
+static int
+cv1800b_usb_phy_parse_dt(struct cv1800_usb_phy_priv *priv, struct device *dev)
+{
+	const char *role;
+
+	if (!of_property_read_string(dev->of_node, "dr_role", &role)) {
+		if (!strcmp(role, "host")) {
+			priv->role = CV1800_USB_PHY_HOST;
+		} else if (!strcmp(role, "device")) {
+			priv->role = CV1800_USB_PHY_DEVICE;
+		} else {
+			dev_err(dev, "invalid dr_role %s", role);
+			return -EINVAL;
+		}
+	} else {
+		priv->role = CV1800_USB_PHY_DEVICE;
+	}
+
+	return 0;
+}
+
+static int cv1800_usb_phy_probe(struct platform_device *pdev)
+{
+	struct cv1800_usb_phy_priv *priv;
+	struct phy_provider *provider;
+	struct device *dev = &pdev->dev;
+	struct phy *phy;
+	int ret;
+
+	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+
+	ret = cv1800b_usb_phy_parse_dt(priv, dev);
+	if (ret)
+		return dev_err_probe(dev, ret, "failed to parse dt");
+
+	priv->regs = devm_platform_ioremap_resource_byname(pdev, "phy");
+	if (IS_ERR(priv->regs))
+		return dev_err_probe(dev, PTR_ERR(priv->regs),
+				     "failed to map phy registers");
+
+	priv->pinreg = devm_platform_ioremap_resource_byname(pdev, "pin");
+	if (IS_ERR(priv->pinreg))
+		return dev_err_probe(dev, PTR_ERR(priv->pinreg),
+				     "failed to map pin register");
+
+	priv->clk_apb = devm_clk_get(dev, "apb");
+	if (IS_ERR(priv->clk_apb))
+		return dev_err_probe(dev, PTR_ERR(priv->clk_apb),
+				     "failed to get apb clock");
+
+	priv->clk_125m = devm_clk_get(dev, "125m");
+	if (IS_ERR(priv->clk_125m))
+		return dev_err_probe(dev, PTR_ERR(priv->clk_125m),
+				     "failed to get 125m clock");
+
+	priv->clk_33k = devm_clk_get(dev, "33k");
+	if (IS_ERR(priv->clk_33k))
+		return dev_err_probe(dev, PTR_ERR(priv->clk_33k),
+				     "failed to get 33k clock");
+
+	priv->clk_12m = devm_clk_get(dev, "12m");
+	if (IS_ERR(priv->clk_12m))
+		return dev_err_probe(dev, PTR_ERR(priv->clk_12m),
+				     "failed to get 12m clock");
+
+	phy = devm_phy_create(dev, NULL, &cv1800_usb_phy_ops);
+	if (IS_ERR(phy))
+		return dev_err_probe(dev, PTR_ERR(phy),
+				     "cannot create phy");
+
+	provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
+
+	phy_set_drvdata(phy, priv);
+
+	return PTR_ERR_OR_ZERO(provider);
+}
+
+static const struct of_device_id cv1800_usb_phy_of_match_table[] = {
+	{ .compatible = "sophgo,cv1800-usb-phy" },
+	{ },
+};
+
+static struct platform_driver cv1800_usb_phy_platform_driver = {
+	.driver = {
+		.name = "cv1800-usb-phy",
+		.of_match_table = cv1800_usb_phy_of_match_table,
+	},
+	.probe = cv1800_usb_phy_probe,
+};
+
+module_platform_driver(cv1800_usb_phy_platform_driver);
+
+MODULE_DESCRIPTION("Sophgo CV1800 USB PHY Driver");
+MODULE_AUTHOR("Yao Zi <ziyao@disroot.org>");
+MODULE_LICENSE("GPL");
-- 
2.45.2


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Re: [PATCH 1/3] dt-bindings: phy: add YAML schema for cv1800-usb-phy driver bindings

[Krzysztof Kozlowski]

On 08/07/2024 14:08, Yao Zi wrote:
> cv1800-usb-phy driver supports USB 2.0 phys integrated in Sophgo
> Cv1800/SG200x SoCs. Add YAML schema for its binding.
> 
> Signed-off-by: Yao Zi <ziyao@disroot.org>

A nit, subject: drop second/last, redundant "bindings". The
"dt-bindings" prefix is already stating that these are bindings.
See also:
https://elixir.bootlin.com/linux/v6.7-rc8/source/Documentation/devicetree/bindings/submitting-patches.rst#L18



> +properties:
> +  compatible:
> +    enum:
> +      - sophgo,cv1800-usb-phy
> +
> +  reg:
> +    maxItems: 2
> +
> +  reg-names:
> +    items:
> +      - const: phy
> +      - const: pin
> +
> +  clocks:
> +    maxItems: 4
> +
> +  clock-names:
> +    items:
> +      - const: apb
> +      - const: 125m
> +      - const: 33k
> +      - const: 12m

All these three should have rather some logical name, not frequency.

> +
> +  "#phy-cells":
> +    const: 0
> +
> +  dr_role:

No underscores in node names, missing vendor prefix (unless it is
generic property), missing description.

Please do not invent new properties like this. You probably wanted to
reference usb-drd?


Best regards,
Krzysztof


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Re: [PATCH 2/3] riscv: dts: sophgo: add nodes for USB phy and controller

[Krzysztof Kozlowski]

On 08/07/2024 14:08, Yao Zi wrote:
>  
> +		usb_phy: usb-phy@3006000 {
> +			compatible = "sophgo,cv1800-usb-phy";
> +			reg = <0x3006000 0x60>, <0x3000048 0x4>;
> +			reg-names = "phy", "pin";
> +			clocks = <&clk CLK_APB_USB>,
> +				 <&clk CLK_USB_125M>,
> +				 <&clk CLK_USB_33K>,
> +				 <&clk CLK_USB_12M>;
> +			clock-names = "apb", "125m", "33k", "12m";

Why are not you using dr_role property here?

Best regards,
Krzysztof


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Re: [PATCH 1/3] dt-bindings: phy: add YAML schema for cv1800-usb-phy driver bindings

[Inochi Amaoto]

On Mon, Jul 08, 2024 at 12:08:28PM GMT, Yao Zi wrote:
> cv1800-usb-phy driver supports USB 2.0 phys integrated in Sophgo
> Cv1800/SG200x SoCs. Add YAML schema for its binding.
> 
> Signed-off-by: Yao Zi <ziyao@disroot.org>
> ---
>  .../bindings/phy/sophgo,cv1800-usb-phy.yaml   | 67 +++++++++++++++++++
>  1 file changed, 67 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/phy/sophgo,cv1800-usb-phy.yaml
> 
> diff --git a/Documentation/devicetree/bindings/phy/sophgo,cv1800-usb-phy.yaml b/Documentation/devicetree/bindings/phy/sophgo,cv1800-usb-phy.yaml
> new file mode 100644
> index 000000000000..0403d899e23b
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/sophgo,cv1800-usb-phy.yaml
> @@ -0,0 +1,67 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +# Copyright 2019 BayLibre, SAS
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/phy/sophgo,cv1800-usb-phy.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Sophgo CV1800 USB PHY
> +
> +maintainers:
> +  - Yao Zi <ziyao@disroot.org>
> +
> +properties:
> +  compatible:
> +    enum:
> +      - sophgo,cv1800-usb-phy
> +
> +  reg:
> +    maxItems: 2
> +
> +  reg-names:
> +    items:
> +      - const: phy
> +      - const: pin

drop pin, cv1800 series does not support this.

> +
> +  clocks:
> +    maxItems: 4
> +
> +  clock-names:
> +    items:
> +      - const: apb
> +      - const: 125m
> +      - const: 33k
> +      - const: 12m
> +
> +  "#phy-cells":
> +    const: 0
> +
> +  dr_role:
> +    enum:
> +      - host
> +      - device

cv181x series have otg support. For board with OTG,
it should be properly handled.

> +
> +required:
> +  - compatible
> +  - reg
> +  - reg-names
> +  - clocks
> +  - clock-names
> +  - "#phy-cells"
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/clock/sophgo,cv1800.h>
> +    usb_phy: usb-phy@3006000 {
> +        compatible = "sophgo,cv1800-usb-phy";
> +        reg = <0x300600 0x60>, <0x3000048 0x4>;
> +        reg-names = "phy", "pin";
> +        clocks = <&clk CLK_APB_USB>,
> +                 <&clk CLK_USB_125M>,
> +                 <&clk CLK_USB_33K>,
> +                 <&clk CLK_USB_12M>;
> +        clock-names = "apb", "125m", "33k", "12m";
> +        #phy-cells = <0>;
> +    };
> -- 
> 2.45.2
> 

You patch is duplicated, I have sumbitted patches 
month ago and still needs some time to figure out 
the best topology. Phy driver belongs to syscon,
which make things kind of complex.

https://lore.kernel.org/all/IA1PR20MB4953C1876484E149AA390DD5BB1D2@IA1PR20MB4953.namprd20.prod.outlook.com/#t

Regards,
Inochi

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Re: [PATCH 1/3] dt-bindings: phy: add YAML schema for cv1800-usb-phy driver bindings

[Chen Wang]

On 2024/7/9 6:23, Inochi Amaoto wrote:
[......]
> You patch is duplicated, I have sumbitted patches
> month ago and still needs some time to figure out
> the best topology. Phy driver belongs to syscon,
> which make things kind of complex.
>
> https://lore.kernel.org/all/IA1PR20MB4953C1876484E149AA390DD5BB1D2@IA1PR20MB4953.namprd20.prod.outlook.com/#t
>
> Regards,
> Inochi

hi, Yao,

Thanks for your contribution.

Just FYI, we are archiving and tracking all PR status about sophgo 
products at https://github.com/sophgo/linux/wiki.

Regards,

Chen


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Re: [PATCH 1/3] dt-bindings: phy: add YAML schema for cv1800-usb-phy driver bindings

[Yao Zi]

On Tue, Jul 09, 2024 at 06:23:58AM +0800, Inochi Amaoto wrote:
> On Mon, Jul 08, 2024 at 12:08:28PM GMT, Yao Zi wrote:
> > cv1800-usb-phy driver supports USB 2.0 phys integrated in Sophgo
> > Cv1800/SG200x SoCs. Add YAML schema for its binding.
> > 
> > Signed-off-by: Yao Zi <ziyao@disroot.org>
> > ---
> >  .../bindings/phy/sophgo,cv1800-usb-phy.yaml   | 67 +++++++++++++++++++
> >  1 file changed, 67 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/phy/sophgo,cv1800-usb-phy.yaml
> > 
> > diff --git a/Documentation/devicetree/bindings/phy/sophgo,cv1800-usb-phy.yaml b/Documentation/devicetree/bindings/phy/sophgo,cv1800-usb-phy.yaml
> > new file mode 100644
> > index 000000000000..0403d899e23b
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/phy/sophgo,cv1800-usb-phy.yaml
> > @@ -0,0 +1,67 @@
> > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> > +# Copyright 2019 BayLibre, SAS
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/phy/sophgo,cv1800-usb-phy.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Sophgo CV1800 USB PHY
> > +
> > +maintainers:
> > +  - Yao Zi <ziyao@disroot.org>
> > +
> > +properties:
> > +  compatible:
> > +    enum:
> > +      - sophgo,cv1800-usb-phy
> > +
> > +  reg:
> > +    maxItems: 2
> > +
> > +  reg-names:
> > +    items:
> > +      - const: phy
> > +      - const: pin
> 
> drop pin, cv1800 series does not support this.
> 
> > +
> > +  clocks:
> > +    maxItems: 4
> > +
> > +  clock-names:
> > +    items:
> > +      - const: apb
> > +      - const: 125m
> > +      - const: 33k
> > +      - const: 12m
> > +
> > +  "#phy-cells":
> > +    const: 0
> > +
> > +  dr_role:
> > +    enum:
> > +      - host
> > +      - device
> 
> cv181x series have otg support. For board with OTG,
> it should be properly handled.
> 
> > +
> > +required:
> > +  - compatible
> > +  - reg
> > +  - reg-names
> > +  - clocks
> > +  - clock-names
> > +  - "#phy-cells"
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > +  - |
> > +    #include <dt-bindings/clock/sophgo,cv1800.h>
> > +    usb_phy: usb-phy@3006000 {
> > +        compatible = "sophgo,cv1800-usb-phy";
> > +        reg = <0x300600 0x60>, <0x3000048 0x4>;
> > +        reg-names = "phy", "pin";
> > +        clocks = <&clk CLK_APB_USB>,
> > +                 <&clk CLK_USB_125M>,
> > +                 <&clk CLK_USB_33K>,
> > +                 <&clk CLK_USB_12M>;
> > +        clock-names = "apb", "125m", "33k", "12m";
> > +        #phy-cells = <0>;
> > +    };
> > -- 
> > 2.45.2
> > 
> 
> You patch is duplicated, I have sumbitted patches 
> month ago and still needs some time to figure out 
> the best topology. Phy driver belongs to syscon,
> which make things kind of complex.
> 
> https://lore.kernel.org/all/IA1PR20MB4953C1876484E149AA390DD5BB1D2@IA1PR20MB4953.namprd20.prod.outlook.com/#t

I didn't check that, sorry for the noise.

Best regards,
Yao Zi

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