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[108.51.35.162]) by smtp.googlemail.com with ESMTPSA id q1sm2346943qti.95.2020.11.07.05.28.52 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 07 Nov 2020 05:28:52 -0800 (PST) Subject: Re: [PATCH 02/32] spi: dw: Add support for 32-bits ctrlr0 layout To: Damien Le Moal , Palmer Dabbelt , linux-riscv@lists.infradead.org, Rob Herring , Frank Rowand , devicetree@vger.kernel.org, Serge Semin , Mark Brown , linux-spi@vger.kernel.org, Stephen Boyd , linux-clk@vger.kernel.org, Linus Walleij , linux-gpio@vger.kernel.org, Philipp Zabel References: <20201107081420.60325-1-damien.lemoal@wdc.com> <20201107081420.60325-3-damien.lemoal@wdc.com> From: Sean Anderson Autocrypt: addr=seanga2@gmail.com; prefer-encrypt=mutual; keydata= mQENBFe74PkBCACoLC5Zq2gwrDcCkr+EPGsT14bsxrW07GiYzQhLCgwnPdEpgU95pXltbFhw 46GfyffABWxHKO2x+3L1S6ZxC5AiKbYXo7lpnTBYjamPWYouz+VJEVjUx9aaSEByBah5kX6a lKFZWNbXLAJh+dE1HFaMi3TQXXaInaREc+aO1F7fCa2zNE75ja+6ah8L4TPRFZ2HKQzve0/Y GXtoRw97qmnm3U36vKWT/m2AiLF619F4T1mHvlfjyd9hrVwjH5h/2rFyroXVXBZHGA9Aj8eN F2si35dWSZlIwXkNu9bXp0/pIu6FD0bI+BEkD5S7aH1G1iAcMFi5Qq2RNa041DfQSDDHABEB AAG0K1NlYW4gR2FsbGFnaGVyIEFuZGVyc29uIDxzZWFuZ2EyQGdtYWlsLmNvbT6JAVcEEwEK AEECGwMFCwkIBwIGFQgJCgsCBBYCAwECHgECF4ACGQEWIQSQYR1bzo1I0gPoYCg+6I/stKEQ bgUCXT+S2AUJB2TlXwAKCRA+6I/stKEQbhNOB/9ooea0hU9Sgh7PBloU6CgaC5mlqPLB7NTp +JkB+nh3Fqhk+qLZwzEynnuDLl6ESpVHIc0Ym1lyF4gT3DsrlGT1h0Gzw7vUwd1+ZfN0CuIx Rn861U/dAUjvbtN5kMBqOI4/5ea+0r7MACcIVnKF/wMXBD8eypHsorT2sJTzwZ6DRCNP70C5 N1ahpqqNmXe0uLdP0pu55JCqhrGw2SinkRMdWyhSxT56uNwIVHGhLTqH7Q4t1N6G1EH626qa SvIJsWlNpll6Y3AYLDw2/Spw/hqieS2PQ/Ky3rPZnvJt7/aSNYsKoFGX0yjkH67Uq8Lx0k1L w8jpXnbEPQN3A2ZJCbeM Message-ID: Date: Sat, 7 Nov 2020 08:28:51 -0500 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.12.0 MIME-Version: 1.0 In-Reply-To: <20201107081420.60325-3-damien.lemoal@wdc.com> Content-Language: en-US X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201107_082856_580027_49C1BDFD X-CRM114-Status: GOOD ( 24.24 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On 11/7/20 3:13 AM, Damien Le Moal wrote: > Synopsis DesignWare DW_apb_ssi version 4 defines a 32-bit layout of > the ctrlr0 register for SPI masters. The layout of ctrlr0 is: > > | 31 .. 23 | 22 .. 21 | 20 .. 16 | > | other stuff | spi_frf | dfs_32 | > > | 15 .. 10 | 9 .. 8 | 7 .. 6 | 5 .. 4 | 3 .. 0 | > | other stuff | tmod | mode | frf | dfs | > > Th main difference of this layout with the 16-bits version is the data > frame format field which resides in bits 16..20 instead of bits 3..0. > > Introduce the DW SPI capability flag DW_SPI_CAP_DFS_32 to let a > platform signal that this layout is in use. Modify > dw_spi_update_config() to test this capability flag to set the data > frame format field at the correct register location. > > Suggested-by: Sean Anderson > Signed-off-by: Damien Le Moal > --- > drivers/spi/spi-dw-core.c | 8 ++++++-- > drivers/spi/spi-dw.h | 9 +++++++++ > 2 files changed, 15 insertions(+), 2 deletions(-) > > diff --git a/drivers/spi/spi-dw-core.c b/drivers/spi/spi-dw-core.c > index 2e50cc0a9291..841c85247f01 100644 > --- a/drivers/spi/spi-dw-core.c > +++ b/drivers/spi/spi-dw-core.c > @@ -311,8 +311,12 @@ void dw_spi_update_config(struct dw_spi *dws, struct spi_device *spi, > u32 speed_hz; > u16 clk_div; > > - /* CTRLR0[ 4/3: 0] Data Frame Size */ > - cr0 |= (cfg->dfs - 1); > + if (!(dws->caps & DW_SPI_CAP_DFS_32)) > + /* CTRLR0[ 4/3: 0] Data Frame Size */ > + cr0 |= (cfg->dfs - 1); > + else > + /* CTRLR0[20: 16] Data Frame Size */ > + cr0 |= (cfg->dfs - 1) << DWC_APB_CTRLR0_32_DFS_OFFSET; > > if (!(dws->caps & DW_SPI_CAP_DWC_SSI)) > /* CTRLR0[ 9:8] Transfer Mode */ > diff --git a/drivers/spi/spi-dw.h b/drivers/spi/spi-dw.h > index faf40cb66498..48a11a51a407 100644 > --- a/drivers/spi/spi-dw.h > +++ b/drivers/spi/spi-dw.h > @@ -9,6 +9,7 @@ > #include > #include > #include > +#include > > /* Register offsets */ > #define DW_SPI_CTRLR0 0x00 > @@ -72,6 +73,13 @@ > #define DWC_SSI_CTRLR0_FRF_OFFSET 6 > #define DWC_SSI_CTRLR0_DFS_OFFSET 0 > > +/* > + * Bit fields in CTRLR0 for DWC_apb_ssi v4 32-bits ctrlr0. > + * Based on DW_apb_ssi Databook v4.02a. > + */ > +#define DWC_APB_CTRLR0_32_DFS_OFFSET 16 > +#define DWC_APB_CTRLR0_32_DFS_MASK GENMASK(20, 16) > + > /* > * For Keem Bay, CTRLR0[31] is used to select controller mode. > * 0: SSI is slave > @@ -121,6 +129,7 @@ enum dw_ssi_type { > #define DW_SPI_CAP_CS_OVERRIDE BIT(0) > #define DW_SPI_CAP_KEEMBAY_MST BIT(1) > #define DW_SPI_CAP_DWC_SSI BIT(2) > +#define DW_SPI_CAP_DFS_32 BIT(3) > > /* Slave spi_transfer/spi_mem_op related */ > struct dw_spi_cfg { > Reviewed-by: Sean Anderson _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv