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Thu, 14 Dec 2023 08:34:53 +0800 From: JeeHeng Sia To: Emil Renner Berthing , "kernel@esmil.dk" , "robh+dt@kernel.org" , "krzysztof.kozlowski+dt@linaro.org" , "krzk@kernel.org" , "conor+dt@kernel.org" , "paul.walmsley@sifive.com" , "palmer@dabbelt.com" , "aou@eecs.berkeley.edu" , "daniel.lezcano@linaro.org" , "tglx@linutronix.de" , "conor@kernel.org" , "anup@brainfault.org" , "gregkh@linuxfoundation.org" , "jirislaby@kernel.org" , "michal.simek@amd.com" , Michael Zhu , "drew@beagleboard.org" CC: "devicetree@vger.kernel.org" , "linux-riscv@lists.infradead.org" , "linux-kernel@vger.kernel.org" , Leyfoon Tan Subject: RE: [PATCH v3 6/6] riscv: dts: starfive: Add initial StarFive JH8100 device tree Thread-Topic: [PATCH v3 6/6] riscv: dts: starfive: Add initial StarFive JH8100 device tree Thread-Index: AQHaJFAfN2r53q/6u0mikZZoJRWxOLCfEf+AgAeiAoCAAUw4MA== Date: Thu, 14 Dec 2023 00:34:53 +0000 Message-ID: References: <20231201121410.95298-1-jeeheng.sia@starfivetech.com> <20231201121410.95298-7-jeeheng.sia@starfivetech.com> In-Reply-To: Accept-Language: en-US, zh-CN Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-exchange-transport-fromentityheader: Hosted x-originating-ip: [202.188.176.82] x-yovoleruleagent: yovoleflag MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231213_163527_639245_4900D530 X-CRM114-Status: GOOD ( 16.47 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org > -----Original Message----- > From: Emil Renner Berthing > Sent: Wednesday, December 13, 2023 8:39 PM > To: Emil Renner Berthing ; JeeHeng Sia ; kernel@esmil.dk; > robh+dt@kernel.org; krzysztof.kozlowski+dt@linaro.org; krzk@kernel.org; conor+dt@kernel.org; paul.walmsley@sifive.com; > palmer@dabbelt.com; aou@eecs.berkeley.edu; daniel.lezcano@linaro.org; tglx@linutronix.de; conor@kernel.org; > anup@brainfault.org; gregkh@linuxfoundation.org; jirislaby@kernel.org; michal.simek@amd.com; Michael Zhu > ; drew@beagleboard.org > Cc: devicetree@vger.kernel.org; linux-riscv@lists.infradead.org; linux-kernel@vger.kernel.org; Leyfoon Tan > > Subject: Re: [PATCH v3 6/6] riscv: dts: starfive: Add initial StarFive JH8100 device tree > > Emil Renner Berthing wrote: > > Sia Jee Heng wrote: > > > Add initial device tree for the StarFive JH8100 RISC-V SoC. > > > > > > Signed-off-by: Sia Jee Heng > > > Reviewed-by: Ley Foon Tan > > > > Looks good to me, thanks. > > > > Acked-by: Emil Renner Berthing > > I just learned that this JH8100 is not actually a real SoC yet but just an FPGA > implementation, and no indication that that's actually a product that will be > mass produced. Hence a lot of details may change before it becomes a real > SoC/product people can buy, so let's not add this device tree yet before > everything is set in silicon. > > Please consider my Acked-by abeve revoked. > > Sia Jee Heng: With that said I still think it's super awesome that you're > beginning upstreaming support for your new SoCs early. I wish more SoC vendors > would follow your example. Hi Emil, I am not sure what you mean. We verified on FPGA & Emulator, and the logic is pretty much close to the real silicon. I did mention that in the cover letter as well. I am new to Linux, so I am wondering if there is a Linux upstream guideline mentioning that pre-silicon software is not allowed to upstream? Hope there is an updated Linux upstream guideline that benefit other vendors. > > /Emil _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv