From: dlustig@nvidia.com (Daniel Lustig)
To: linux-riscv@lists.infradead.org
Subject: [PATCH] riscv/barrier: Define __smp_{store_release,load_acquire}
Date: Tue, 27 Feb 2018 14:20:37 -0800 [thread overview]
Message-ID: <e482049c-70b5-3b4f-a818-0740bec9a4fa@nvidia.com> (raw)
In-Reply-To: <mhng-d0fc25e5-9a3f-4988-9260-3d584b8f4606@palmer-si-x1c4>
On 2/27/2018 10:21 AM, Palmer Dabbelt wrote:
> On Mon, 26 Feb 2018 18:24:11 PST (-0800), parri.andrea at gmail.com wrote:
>> Introduce __smp_{store_release,load_acquire}, and rely on the generic
>> definitions for smp_{store_release,load_acquire}. This avoids the use
>> of full ("rw,rw") fences on SMP.
>>
>> Signed-off-by: Andrea Parri <parri.andrea@gmail.com>
>> ---
>> ?arch/riscv/include/asm/barrier.h | 15 +++++++++++++++
>> ?1 file changed, 15 insertions(+)
>>
>> diff --git a/arch/riscv/include/asm/barrier.h b/arch/riscv/include/asm/barrier.h
>> index 5510366d169ae..d4628e4b3a5ea 100644
>> --- a/arch/riscv/include/asm/barrier.h
>> +++ b/arch/riscv/include/asm/barrier.h
>> @@ -38,6 +38,21 @@
>> ?#define __smp_rmb()??? RISCV_FENCE(r,r)
>> ?#define __smp_wmb()??? RISCV_FENCE(w,w)
>>
>> +#define __smp_store_release(p, v)??????????????????? \
>> +do {??????????????????????????????????? \
>> +??? compiletime_assert_atomic_type(*p);??????????????? \
>> +??? RISCV_FENCE(rw,w);??????????????????????? \
>> +??? WRITE_ONCE(*p, v);??????????????????????? \
>> +} while (0)
>> +
>> +#define __smp_load_acquire(p)??????????????????????? \
>> +({??????????????????????????????????? \
>> +??? typeof(*p) ___p1 = READ_ONCE(*p);??????????????? \
>> +??? compiletime_assert_atomic_type(*p);??????????????? \
>> +??? RISCV_FENCE(r,rw);??????????????????????? \
>> +??? ___p1;??????????????????????????????? \
>> +})
>> +
>> ?/*
>> ? * This is a very specific barrier: it's currently only used in two places in
>> ? * the kernel, both in the scheduler.? See include/linux/spinlock.h for the two
>
> I'm adding Daniel just in case I misunderstood what's going on here,
> but these look good to me. As this is a non-trivial memory model
> change I'm going to let it bake in linux-next for a bit just so it
> gets some visibility.
Looks good to me too. In particular, it also covers the
Write->release(p)->acquire(p)->Write ordering that we were debating
in the broader LKMM thread, which is good.
Dan
>
> Thanks
next prev parent reply other threads:[~2018-02-27 22:20 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-02-27 2:24 [PATCH] riscv/barrier: Define __smp_{store_release,load_acquire} Andrea Parri
2018-02-27 18:21 ` Palmer Dabbelt
2018-02-27 22:20 ` Daniel Lustig [this message]
2018-02-28 0:15 ` Andrea Parri
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