From: Paul Walmsley <pjw@kernel.org>
To: Andy Chiu <tchiu@tenstorrent.com>
Cc: Paul Walmsley <pjw@kernel.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Alexandre Ghiti <alex@ghiti.fr>,
linux-riscv@lists.infradead.org, andybnac@gmail.com,
Anton Blanchard <antonb@tenstorrent.com>,
dfustini@oss.tenstorrent.com, greentime.hu@sifive.com
Subject: Re: [PATCH v1] riscv: skip software algning code for HAVE_EFFICIENT_UNALIGNED_ACCESS
Date: Tue, 1 Sep 2026 17:03:57 -0600 (MDT) [thread overview]
Message-ID: <e68701c4-2e91-8bc2-77af-9092eda7189f@kernel.org> (raw)
In-Reply-To: <20260901192334.3543340-1-tchiu@tenstorrent.com>
Hi,
On Tue, 1 Sep 2026, Andy Chiu wrote:
> We can jump straight into the copy loop if the kernel is compiled for a
> hardware that natively supports misaligned access. The user copy
> bandwidth improvement on K3 and Ascaolon is shown as below:
>
> Misaligned user copy, size: 512B (offset: [0:15] except 0, 8)
> BW Improvement | Write | Read |
> K3 | 6.19% | 3.43% |
> Ascalon | 10.0% | 11.4% |
>
> Aligned user copy, size: 512B (offset: 0, 8)
> BW Improvement | Write | Read |
> K3 | 1.69% | 0.90% |
> Ascalon | 1.25% | 3.32% |
>
> Suggested-by: Anton Blanchard <antonb@tenstorrent.com>
> Signed-off-by: Andy Chiu <tchiu@tenstorrent.com>
> ---
> arch/riscv/lib/uaccess.S | 5 ++++-
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/arch/riscv/lib/uaccess.S b/arch/riscv/lib/uaccess.S
> index 4efea1b3326c..cf8586a937de 100644
> --- a/arch/riscv/lib/uaccess.S
> +++ b/arch/riscv/lib/uaccess.S
> @@ -76,6 +76,7 @@ SYM_FUNC_START(fallback_scalar_usercopy_sum_enabled)
> li a3, 9*SZREG-1 /* size must >= (word_copy stride + SZREG-1) */
> bltu a2, a3, .Lbyte_copy_tail
>
> +#if !defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
[ ... ]
So I guess this is just targeting the fallback scalar path, and only for
nonportable kernel builds? Is it possible to use the result of dynamic
misaligned access speed detection here, to improve performance for
portable kernels as well?
- Paul
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next prev parent reply other threads:[~2026-09-01 23:04 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-01 19:23 [PATCH v1] riscv: skip software algning code for HAVE_EFFICIENT_UNALIGNED_ACCESS Andy Chiu
2026-09-01 23:03 ` Paul Walmsley [this message]
2026-09-02 0:37 ` patchwork-bot+linux-riscv
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