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Wed, 5 Oct 2022 05:58:18 -0400 (EDT) X-Mailer: MessagingEngine.com Webmail Interface User-Agent: Cyrus-JMAP/3.7.0-alpha0-1015-gaf7d526680-fm-20220929.001-gaf7d5266 Mime-Version: 1.0 Message-Id: In-Reply-To: References: <20221003223222.448551-1-prabhakar.mahadev-lad.rj@bp.renesas.com> <20221003223222.448551-3-prabhakar.mahadev-lad.rj@bp.renesas.com> Date: Wed, 05 Oct 2022 11:57:58 +0200 From: "Arnd Bergmann" To: "Conor Dooley" , Prabhakar Cc: "Geert Uytterhoeven" , "Paul Walmsley" , "Palmer Dabbelt" , "Albert Ou" , "Rob Herring" , "Krzysztof Kozlowski" , "Magnus Damm" , =?UTF-8?Q?Heiko_St=C3=BCbner?= , guoren , "Conor.Dooley" , "Philipp Tomsich" , "Nathan Chancellor" , "Atish Patra" , "Anup Patel" , Linux-Renesas , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, "Biju Das" , "Lad, Prabhakar" Subject: Re: [RFC PATCH v2 2/2] soc: renesas: Add L2 cache management for RZ/Five SoC X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221005_025825_732878_7A43BD89 X-CRM114-Status: GOOD ( 10.78 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Tue, Oct 4, 2022, at 7:42 PM, Conor Dooley wrote: > On Mon, Oct 03, 2022 at 11:32:22PM +0100, Prabhakar wrote: >> >> Signed-off-by: Lad Prabhakar >> --- >> arch/riscv/include/asm/cacheflush.h | 8 + >> arch/riscv/include/asm/errata_list.h | 2 + >> arch/riscv/include/asm/sbi.h | 1 + >> arch/riscv/mm/dma-noncoherent.c | 20 ++ > > Stupid question maybe, but I assume you mixed the driver addition and > the changes to arch/riscv for the sake of easily creating the RFC? > >> drivers/soc/renesas/Makefile | 4 + >> drivers/soc/renesas/rzf/Makefile | 3 + >> drivers/soc/renesas/rzf/ax45mp_cache.c | 365 +++++++++++++++++++++++++ >> drivers/soc/renesas/rzf/rzf_sbi.h | 27 ++ My feeling is that L2 cache behavior should live in arch/riscv rather than drivers/soc/, since this is not specific to a SoC family but rather the CPU core. I would also expect that the actual implementation and DT binding can be shared with non-renesas SoCs using the same CPU core. Arnd _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv