From: <Conor.Dooley@microchip.com>
To: <heiko@sntech.de>, <palmer@rivosinc.com>
Cc: <linux-riscv@lists.infradead.org>, <nathan@kernel.org>,
<mail@conchuod.ie>, <atishp@atishpatra.org>,
<ajones@ventanamicro.com>, <anup@brainfault.org>, <lkp@intel.com>
Subject: Re: [PATCH] RISC-V: move riscv_cbom_block_size to the correct #ifdef block
Date: Wed, 14 Sep 2022 19:32:01 +0000 [thread overview]
Message-ID: <e7e5a415-e097-a56e-880b-fa0488d2b73a@microchip.com> (raw)
In-Reply-To: <20220914143648.74022-1-heiko@sntech.de>
On 14/09/2022 15:36, Heiko Stuebner wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> riscv_cbom_block_size is used by all current non-coherent dma operations,
> not only the zicbom variant. So move it over the block also containing
> the riscv_noncoherent_supported() prototype.
>
> Fixes: 8f7e001e0325 ("RISC-V: Clean up the Zicbom block size probing")
> Reported-by: kernel test robot <lkp@intel.com>
> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
I accidentally fetched palmers repo rather than riscv & noticed he
pushed a fix there for this too:
https://git.kernel.org/pub/scm/linux/kernel/git/palmer/linux.git/commit/?h=zicbom-fix
I think Palmer's solution is slightly nicer, but to me either makes
little difference, just getting things squared away for 6.0 is all
I care about at this point.
Either this or the one on Palmer's branch is:
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
> ---
> arch/riscv/include/asm/cacheflush.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/riscv/include/asm/cacheflush.h b/arch/riscv/include/asm/cacheflush.h
> index a89c005b4bbf..5c16d901d3da 100644
> --- a/arch/riscv/include/asm/cacheflush.h
> +++ b/arch/riscv/include/asm/cacheflush.h
> @@ -43,13 +43,13 @@ void flush_icache_mm(struct mm_struct *mm, bool local);
> #endif /* CONFIG_SMP */
>
> #ifdef CONFIG_RISCV_ISA_ZICBOM
> -extern unsigned int riscv_cbom_block_size;
> void riscv_init_cbom_blocksize(void);
> #else
> static inline void riscv_init_cbom_blocksize(void) { }
> #endif
>
> #ifdef CONFIG_RISCV_DMA_NONCOHERENT
> +extern unsigned int riscv_cbom_block_size;
> void riscv_noncoherent_supported(void);
> #endif
>
> --
> 2.35.1
>
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next prev parent reply other threads:[~2022-09-14 19:32 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-14 14:36 [PATCH] RISC-V: move riscv_cbom_block_size to the correct #ifdef block Heiko Stuebner
2022-09-14 14:46 ` Anup Patel
2022-09-14 14:54 ` Conor.Dooley
2022-09-14 14:56 ` Anup Patel
2022-09-14 14:58 ` Heiko Stuebner
2022-09-14 19:32 ` Conor.Dooley [this message]
2022-09-14 22:19 ` Heiko Stuebner
2022-09-15 17:09 ` Palmer Dabbelt
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