From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 66BCDCA5FAD for ; Wed, 30 Sep 2026 00:21:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:Content-Type: Content-Transfer-Encoding:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:Message-ID:In-Reply-To: Subject:cc:To:From:Date:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=wFz7QVWffCF7gMk+LuqT7PP0CwSWtDONk4AYu91KEYA=; b=hzEhXElGHBCHYvhxPweVDMexpf GF8uXmZCuOphpdmecjhaKnpoC6nhk2ax/dESyPMrPxXqn1EEZircsRaRuZ0t/5TE1FnxTw4lDNFIs puf3Xg11YcluGqwRptetjIquUMculvtJLZFms/gkDAgGCiNCWz43ZOXCSReT8qOy6hxnLO4AQCinN Q0LVbrHy1ObRolNoL0+tXh6ZC4/o6WPJ4zxoowVXxUuvSTPn3VxG1MM9kFAAUUsTEgrWYhEKRJiL8 aM7zuism91hn3Qm7lsLGJKq9rdFmsL/wQwvbGy4RJ1UNr6wS3bKxAGzC8SG/1UgK+sLXmxi/huhcS w3I7bg3g==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.99.1 #2 (Red Hat Linux)) id 1xBi4B-00000004oPB-0crI; Wed, 30 Sep 2026 00:20:59 +0000 Received: from winds.org ([68.75.195.9]) by bombadil.infradead.org with esmtps (Exim 4.99.1 #2 (Red Hat Linux)) id 1xBi47-00000004oNo-04QW; Wed, 30 Sep 2026 00:20:56 +0000 Received: by winds.org (Postfix, from userid 100) id 26A288F95F83; Tue, 29 Sep 2026 20:20:50 -0400 (EDT) Received: from localhost (localhost [127.0.0.1]) by winds.org (Postfix) with ESMTP id 2557E13363343; Tue, 29 Sep 2026 20:20:50 -0400 (EDT) Date: Tue, 29 Sep 2026 20:20:50 -0400 (EDT) From: Byron Stanoszek To: Michal Wilczynski cc: Vinod Koul , Manivannan Sadhasivam , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andrzej Hajda , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Luca Ceresoli , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Andy Yan , Philipp Zabel , Emil Renner Berthing , Hal Feng , Michael Turquette , Stephen Boyd , Heiko Stuebner , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Dominique Belhachemi , Brian Masney , Jerome Brunet , linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-riscv@lists.infradead.org, Marek Szyprowski , Maud Spierings , Graham Markall , Icenowy Zheng , Chaoyi Chen , Joshua Peisach , =?ISO-8859-15?Q?Uwe_Kleine-K=F6nig?= , Krzysztof Kozlowski Subject: Re: [PATCH v5 00/21] drm: starfive: jh7110: Enable display subsystem In-Reply-To: <20260929-jh7110-clean-send-v5-0-82b4d8e3c6c7@samsung.com> Message-ID: References: <20260929-jh7110-clean-send-v5-0-82b4d8e3c6c7@samsung.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260929_172055_152920_21BA96E1 X-CRM114-Status: GOOD ( 15.24 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Tue, 29 Sep 2026, Michal Wilczynski wrote: > This series enables the display subsystem on the StarFive JH7110. > > [...] > - New patch 1 fixes v_HSYNC_POLARITY and v_VSYNC_POLARITY, which have > been swapped in inno-hdmi since the driver was merged. The hardware > puts HSYNC in bit 2 and VSYNC in bit 3, and the driver had them the > other way round. Almost all CEA modes drive both syncs with the same > polarity, so the two writes are indistinguishable and the bug only > shows on a mode whose polarities differ - a band of black rows at the > top of the screen, vsync_end - vsync_start + 1 rows tall. Reported > independently by Dominique Belhachemi, Maud Spierings and Byron > Stanoszek, and confirmed against the RK3128 TRM by Icenowy Zheng, so > this is a Rockchip fix too. > - Added a 201 MHz entry to the JH7110 pre-PLL table for a 2560x1440 > mode Byron Stanoszek runs on a Dell U2711. It is derived the same way > as the neighbouring entries (fbdiv 134, /16, VCO 3.216 GHz) but I have > no sink that asks for it, so it is untested on my hardware. Hi Michal, I confirm that the hsync/vsync polarity and 201 MHz mode are both working on my setup in v5. Tested against 7.3-rc5 with af384d6e0573 and Bo Gan's cache coherency fixes. Thanks again for your work on this series! Tested-by: Byron Stanoszek Best regards, -Byron _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv