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([2601:647:4180:9630::e8c1]) by smtp.gmail.com with ESMTPSA id c17-20020a170902d49100b001e1071cf0bbsm4411011plg.302.2024.04.08.17.04.42 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 08 Apr 2024 17:04:43 -0700 (PDT) Message-ID: Date: Mon, 8 Apr 2024 17:04:41 -0700 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 03/22] drivers/perf: riscv: Read upper bits of a firmware counter Content-Language: en-US To: Andrew Jones Cc: linux-kernel@vger.kernel.org, Palmer Dabbelt , Conor Dooley , Anup Patel , Ajay Kaher , Alexandre Ghiti , Alexey Makhalov , Juergen Gross , kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Rutland , Palmer Dabbelt , Paolo Bonzini , Paul Walmsley , Shuah Khan , virtualization@lists.linux.dev, VMware PV-Drivers Reviewers , Will Deacon , x86@kernel.org References: <20240403080452.1007601-1-atishp@rivosinc.com> <20240403080452.1007601-4-atishp@rivosinc.com> <20240404-89ee7d7f90a5fcc91809065e@orel> From: Atish Patra In-Reply-To: <20240404-89ee7d7f90a5fcc91809065e@orel> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240408_170446_229266_DCAB4231 X-CRM114-Status: GOOD ( 22.22 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On 4/4/24 04:02, Andrew Jones wrote: > On Wed, Apr 03, 2024 at 01:04:32AM -0700, Atish Patra wrote: >> SBI v2.0 introduced a explicit function to read the upper 32 bits >> for any firmware counter width that is longer than 32bits. >> This is only applicable for RV32 where firmware counter can be >> 64 bit. >> >> Reviewed-by: Andrew Jones >> Acked-by: Palmer Dabbelt >> Reviewed-by: Conor Dooley >> Reviewed-by: Anup Patel >> Signed-off-by: Atish Patra >> --- >> drivers/perf/riscv_pmu_sbi.c | 25 ++++++++++++++++++++----- >> 1 file changed, 20 insertions(+), 5 deletions(-) >> >> diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c >> index 3e44d2fb8bf8..babf1b9a4dbe 100644 >> --- a/drivers/perf/riscv_pmu_sbi.c >> +++ b/drivers/perf/riscv_pmu_sbi.c >> @@ -57,6 +57,8 @@ asm volatile(ALTERNATIVE( \ >> PMU_FORMAT_ATTR(event, "config:0-47"); >> PMU_FORMAT_ATTR(firmware, "config:63"); >> >> +static bool sbi_v2_available; >> + >> static struct attribute *riscv_arch_formats_attr[] = { >> &format_attr_event.attr, >> &format_attr_firmware.attr, >> @@ -511,19 +513,29 @@ static u64 pmu_sbi_ctr_read(struct perf_event *event) >> struct hw_perf_event *hwc = &event->hw; >> int idx = hwc->idx; >> struct sbiret ret; >> - union sbi_pmu_ctr_info info; >> u64 val = 0; >> + union sbi_pmu_ctr_info info = pmu_ctr_list[idx]; >> >> if (pmu_sbi_is_fw_event(event)) { >> ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_FW_READ, >> hwc->idx, 0, 0, 0, 0, 0); >> - if (!ret.error) >> - val = ret.value; >> + if (ret.error) >> + return 0; >> + >> + val = ret.value; >> + if (IS_ENABLED(CONFIG_32BIT) && sbi_v2_available && info.width >= 32) { >> + ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_FW_READ_HI, >> + hwc->idx, 0, 0, 0, 0, 0); >> + if (!ret.error) >> + val |= ((u64)ret.value << 32); >> + else >> + WARN_ONCE(1, "Unable to read upper 32 bits of firmware counter error: %d\n", >> + sbi_err_map_linux_errno(ret.error)); > > I don't think we should use sbi_err_map_linux_errno() in this case since > we don't have a 1:1 mapping of SBI errors to Linux errors and we don't > propagate the error as a Linux error. For warnings, it's better to output > the exact SBI error. > Sure. Fixed it. >> + } >> } else { >> - info = pmu_ctr_list[idx]; >> val = riscv_pmu_ctr_read_csr(info.csr); >> if (IS_ENABLED(CONFIG_32BIT)) >> - val = ((u64)riscv_pmu_ctr_read_csr(info.csr + 0x80)) << 31 | val; >> + val |= ((u64)riscv_pmu_ctr_read_csr(info.csr + 0x80)) << 32; >> } >> >> return val; >> @@ -1135,6 +1147,9 @@ static int __init pmu_sbi_devinit(void) >> return 0; >> } >> >> + if (sbi_spec_version >= sbi_mk_version(2, 0)) >> + sbi_v2_available = true; >> + >> ret = cpuhp_setup_state_multi(CPUHP_AP_PERF_RISCV_STARTING, >> "perf/riscv/pmu:starting", >> pmu_sbi_starting_cpu, pmu_sbi_dying_cpu); >> -- >> 2.34.1 >> > > Thanks, > drew _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv