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From: David Laight <David.Laight@ACULAB.COM>
To: "'Clément Léger'" <cleger@rivosinc.com>,
	"Conor Dooley" <conor@kernel.org>
Cc: "Paul Walmsley" <paul.walmsley@sifive.com>,
	"Palmer Dabbelt" <palmer@dabbelt.com>,
	"Albert Ou" <aou@eecs.berkeley.edu>,
	"Atish Patra" <atishp@rivosinc.com>,
	"Andrew Jones" <ajones@ventanamicro.com>,
	"Evan Green" <evan@rivosinc.com>,
	"Björn Topel" <bjorn@rivosinc.com>,
	"linux-riscv@lists.infradead.org"
	<linux-riscv@lists.infradead.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"Ron Minnich" <rminnich@gmail.com>,
	"Daniel Maslowski" <cyrevolt@googlemail.com>
Subject: RE: [PATCH 0/7] Add support to handle misaligned accesses in S-mode
Date: Wed, 4 Oct 2023 08:26:49 +0000	[thread overview]
Message-ID: <eb9dcaaf313642b096d68df4b92e7466@AcuMS.aculab.com> (raw)
In-Reply-To: <8ce6cd97-6d63-4174-a290-40690c81e205@rivosinc.com>

From: Clément Léger
> Sent: 02 October 2023 08:40
> 
> On 30/09/2023 11:23, Conor Dooley wrote:
> > On Tue, Sep 26, 2023 at 05:03:09PM +0200, Clément Léger wrote:
> >> Since commit 61cadb9 ("Provide new description of misaligned load/store
> >> behavior compatible with privileged architecture.") in the RISC-V ISA
> >> manual, it is stated that misaligned load/store might not be supported.
> >> However, the RISC-V kernel uABI describes that misaligned accesses are
> >> supported.
...

That it just really horrid.
If the cpu is going to trap misaligned accesses then you want
The compiler generated code (ie packed data) not to generate
misaligned accesses.
So you have to change the kernel uABI.

OTOH if you known that such accesses won't fault and will be
not really slower than aligned accesses then optimised versions
of some functions (like memcpy and checksums) can use misaligned
accesses.

	David

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  parent reply	other threads:[~2023-10-04  8:27 UTC|newest]

Thread overview: 29+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-09-26 15:03 [PATCH 0/7] Add support to handle misaligned accesses in S-mode Clément Léger
2023-09-26 15:03 ` [PATCH 1/7] riscv: remove unused functions in traps_misaligned.c Clément Léger
2023-09-26 15:03 ` [PATCH 2/7] riscv: add support for misaligned handling in S-mode Clément Léger
2023-09-26 15:03 ` [PATCH 3/7] riscv: report perf event for misaligned fault Clément Léger
2023-09-26 15:03 ` [PATCH 4/7] riscv: add floating point insn support to misaligned access emulation Clément Léger
2023-09-26 15:03 ` [PATCH 5/7] riscv: add support for sysctl unaligned_enabled control Clément Léger
2023-09-26 15:03 ` [PATCH 6/7] riscv: report misaligned accesses emulation to hwprobe Clément Léger
2023-09-26 21:57   ` Evan Green
2023-09-28  7:46     ` Clément Léger
2023-09-28 16:51       ` Evan Green
2023-10-03  9:50         ` Atish Kumar Patra
2023-09-29  1:02   ` kernel test robot
2023-09-26 15:03 ` [PATCH 7/7] riscv: add support for PR_SET_UNALIGN and PR_GET_UNALIGN Clément Léger
2023-09-26 21:43 ` [PATCH 0/7] Add support to handle misaligned accesses in S-mode Evan Green
2023-09-28  7:49   ` Clément Léger
2023-09-28 16:48     ` Evan Green
2023-10-03  8:40       ` Atish Kumar Patra
2023-10-03 15:39         ` ron minnich
2023-09-30  9:23 ` Conor Dooley
2023-10-02  7:40   ` Clément Léger
2023-10-02 10:49     ` Conor Dooley
2023-10-02 11:18       ` Clément Léger
2023-10-02 15:32         ` ron minnich
2023-10-02 22:22           ` Jessica Clarke
2023-10-03 15:37             ` ron minnich
2023-10-03  8:12           ` Clément Léger
2023-10-04  8:26     ` David Laight [this message]
2023-10-04 10:03       ` Clément Léger
2023-10-04 14:10         ` David Laight

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