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Tue, 12 Apr 2022 11:29:32 -0700 (PDT) Message-ID: Date: Tue, 12 Apr 2022 19:29:31 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.7.0 Subject: Re: [PATCH v2 5/9] dt-bindings: clk: mpfs: add defines for two new clocks Content-Language: en-US To: Krzysztof Kozlowski , Conor.Dooley@microchip.com, mturquette@baylibre.com, sboyd@kernel.org, aou@eecs.berkeley.edu, paul.walmsley@sifive.com, palmer@rivosinc.com, a.zummo@towertech.it, alexandre.belloni@bootlin.com, robh+dt@kernel.org, krzk+dt@kernel.org Cc: Daire.McNamara@microchip.com, linux-rtc@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-riscv@lists.infradead.org References: <20220411085916.941433-1-conor.dooley@microchip.com> <20220411085916.941433-6-conor.dooley@microchip.com> <2e1b0207-dfb3-4cc5-d306-d2b0c6ed8cfd@microchip.com> <25feb189-4d97-f9b1-518e-69aae9a274e0@linaro.org> <74695e55-0b59-9236-be19-b02060ad4177@microchip.com> From: Conor Dooley In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220412_112938_464381_86156D39 X-CRM114-Status: GOOD ( 18.51 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On 12/04/2022 18:10, Krzysztof Kozlowski wrote: > On 12/04/2022 14:26, Conor.Dooley@microchip.com wrote: >>>> Additionally MSSPLL is the source for CLK_{CPI,AXI,AHB} so I put it at >>>> the top. I have no particular preference, so if you want them reordered >>>> so that MSSPLL is under RTCREF just say the word :) >>> >>> Hm, are these in the same clock controller (device, not driver)? If yes, >>> then please order them numerically. Pretty often one binding header have >>> IDs for several clock controllers, so then it's a different case. >> >> Not *quite* sure what you mean by device. There is only one SoC that >> this header applies to, but in the actual design the MSSPLL is in one >> block, the RTC divider in another and CLK_CPU -> CLK_CFM in a third. > > By device I meant here part of Soc responsible for clocks which could be > called a self-containing block. Pretty often such block maps to a Linux > "struct device" or some wrapper around it (e.g. clock-controller > device). For example such "self-containing block" has device node in DTS. > > Judging by your description, these will be different blocks / device > nodes in DTS? The way it's implemented is a bit interconnected and none of the three blocks would satisfy a "self contained" constraint. Eg. The rtcref divider's control reg sits between two registers responsible for the CLK_CPU -> CLK_CFM clocks but it's input clock mux is in the same sub-block as the MSSPLL. I guess its better put that each of the three are sub-blocks of a self contained clock controller for the mss core complex. There are several other clock domains on the chip which would have distinct clock controllers & may be added to this header in the future, if letting Linux control them makes any sense. For example, clocks in (and used for the clocking of) the fpga fabric. This controller is a single node in the device tree. Sounds like reordering it numerically makes the most sense then - I'll resend tomorrow if that's okay. Thanks, Conor. _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv