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Sat, 01 Jul 2023 01:22:27 -0700 (PDT) Received: from [192.168.10.214] ([217.169.179.6]) by smtp.gmail.com with ESMTPSA id b27-20020a170906195b00b00991e2b5a27dsm6356217eje.37.2023.07.01.01.22.25 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 01 Jul 2023 01:22:26 -0700 (PDT) Message-ID: Date: Sat, 1 Jul 2023 10:22:25 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.12.0 Subject: Re: [PATCH 3/3] dt-bindings: riscv: sifive: Add SiFive Private L2 cache controller Content-Language: en-US To: Eric Lin Cc: conor@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dslin1010@gmail.com, Zong Li , Nick Hu , Greentime Hu , Palmer Dabbelt , Paul Walmsley References: <20230616063210.19063-1-eric.lin@sifive.com> <20230616063210.19063-4-eric.lin@sifive.com> <2437bda9-bbdb-ad80-7201-1e16e1388890@linaro.org> <8c9ed2d4-83ab-ecc0-a300-e6bc8e2047b6@linaro.org> From: Krzysztof Kozlowski In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230701_012229_426628_75093EAE X-CRM114-Status: GOOD ( 13.63 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On 28/06/2023 18:31, Eric Lin wrote: >>>> >>>>> + - enum: >>>>> + - sifive,pL2Cache0 >>>>> + - sifive,pL2Cache1 >>>> >>>> What is "0" and "1" here? What do these compatibles represent? Why they >>>> do not have any SoC related part? >>> >>> The pL2Cache1 has minor changes in hardware, but it can use the same >>> pl2 cache driver. >> >> Then why aren't they compatible? >> > > The pL2Cache1 has removed some unused bits in the register compared to > pl2Cache0. > From the hardware perspective, they are not compatible but they can > share the same pl2 cache driver in software. So they are compatible... If they were not compatible, you wouldn't be able to use the same match in the driver. > Thus, we would like to keep both. It would be great if you can provide > some suggestions. Thanks. I propose to make them compatible, like every other piece of SoC. I don't see any benefit of having them separate. Best regards, Krzysztof _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv