Re: [PATCH v3 6/7] riscv: dts: starfive: Add initial StarFive JH7110 device tree

Hal Feng
2023-02-01T07:32:26Z

On Thu, 29 Dec 2022 13:25:00 +0800, Icenowy Zheng wrote:
> 在 2022-12-28星期三的 22:48 +0000，Conor Dooley写道：
>> Hey,
>>
>> On Tue, Dec 20, 2022 at 09:12:46AM +0800, Hal Feng wrote:
[...]
>> > +               U74_1: cpu@1 {
>> > +                       compatible = "sifive,u74-mc", "riscv";
>> > +                       reg = <1>;
>> > +                       d-cache-block-size = <64>;
>> > +                       d-cache-sets = <64>;
>> > +                       d-cache-size = <32768>;
>> > +                       d-tlb-sets = <1>;
>> > +                       d-tlb-size = <40>;
>> > +                       device_type = "cpu";
>> > +                       i-cache-block-size = <64>;
>> > +                       i-cache-sets = <64>;
>> > +                       i-cache-size = <32768>;
>> > +                       i-tlb-sets = <1>;
>> > +                       i-tlb-size = <40>;
>> > +                       mmu-type = "riscv,sv39";
>> > +                       next-level-cache = <&ccache>;
>> > +                       riscv,isa = "rv64imafdc";
>>
>> That also begs the question:
>> Do your u74s support RV64GBC, as the (current) SiFive documentation
>> suggests?
>
> It supports RV64GCZbaZbb.
>
> B is not a well-defined thing by specifications, so it should be
> prevented here.

Thank you for your kindly reply.

Best regards,
Hal