Re: [PATCH v3 6/7] riscv: dts: starfive: Add initial StarFive JH7110 device tree

Hal Feng
2023-02-01T07:53:32Z

On Thu, 29 Dec 2022 09:02:15 +0000, Conor Dooley wrote:
> Hey Icenowy, Hal
>
> On 29 December 2022 05:25:00 GMT, Icenowy Zheng <uwu@icenowy.me> wrote:
>>在 2022-12-28星期三的 22:48 +0000，Conor Dooley写道：
>>> Hey,
>>>
>>> On Tue, Dec 20, 2022 at 09:12:46AM +0800, Hal Feng wrote:
[...]
>>> > +               U74_1: cpu@1 {
>>> > +                       compatible = "sifive,u74-mc", "riscv";
>>> > +                       reg = <1>;
>>> > +                       d-cache-block-size = <64>;
>>> > +                       d-cache-sets = <64>;
>>> > +                       d-cache-size = <32768>;
>>> > +                       d-tlb-sets = <1>;
>>> > +                       d-tlb-size = <40>;
>>> > +                       device_type = "cpu";
>>> > +                       i-cache-block-size = <64>;
>>> > +                       i-cache-sets = <64>;
>>> > +                       i-cache-size = <32768>;
>>> > +                       i-tlb-sets = <1>;
>>> > +                       i-tlb-size = <40>;
>>> > +                       mmu-type = "riscv,sv39";
>>> > +                       next-level-cache = <&ccache>;
>>> > +                       riscv,isa = "rv64imafdc";
>>>
>>> That also begs the question:
>>> Do your u74s support RV64GBC, as the (current) SiFive documentation
>>> suggests?
>>
>>It supports RV64GCZbaZbb.
>
> Sweet, thanks.
>
>>B is not a well-defined thing by specifications, so it should be
>>prevented here.
>
> Yah, don't worry - my next question was going to be which bits were supported :)
>
> Hal, can you update the isa string in the next version please?

The current isa description is correct. Please see my reply [1].
Thank you.

[1] https://lore.kernel.org/all/c507e0b2-5ca3-cffe-55d2-873ed8c24e3d@starfivetech.com/

Best regards,
Hal