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From: <Conor.Dooley@microchip.com>
To: <ajones@ventanamicro.com>, <zouyipeng@huawei.com>
Cc: <linux-riscv@lists.infradead.org>, <paul.walmsley@sifive.com>,
	<palmer@dabbelt.com>, <aou@eecs.berkeley.edu>,
	<liaochang1@huawei.com>, <chris.zjh@huawei.com>
Subject: Re: [PATCH v2] riscv: lib: optimize memcmp with ld insn
Date: Mon, 5 Sep 2022 11:58:57 +0000	[thread overview]
Message-ID: <ffaa7ed6-18e9-2344-4bb4-bbaaa42fe3bd@microchip.com> (raw)
In-Reply-To: <20220905114928.4h5fjnydk2jvsxmu@kamzik>

On 05/09/2022 12:49, Andrew Jones wrote:
> 
> I'd prefer an assembly format were the operands are lined up
> 
>    op    r1, r2
>    op    r1, r2
> 
> Unfortunately I don't see much consistency in how to do this among other
> riscv .S files, though, so I'm not sure what to recommend if anything.

Gotta start somewhere for consistency & we can drift to something that
is actually consistent over time /shrug

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  reply	other threads:[~2022-09-05 17:52 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-09-02 11:00 [PATCH v2] riscv: lib: optimize memcmp with ld insn Yipeng Zou
2022-09-05 11:49 ` Andrew Jones
2022-09-05 11:58   ` Conor.Dooley [this message]
2022-09-06  2:15   ` Yipeng Zou

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