* [GIT PULL] RISC-V Patches for the 6.16 Merge Window, Part 3
@ 2025-06-05 7:29 Alexandre Ghiti
2025-06-05 18:06 ` Palmer Dabbelt
0 siblings, 1 reply; 2+ messages in thread
From: Alexandre Ghiti @ 2025-06-05 7:29 UTC (permalink / raw)
To: linux-riscv@lists.infradead.org, Palmer Dabbelt
The following changes since commit dc5240f09bca7b5fc72ad8894d6b9321bce51139:
RISC-V: vDSO: Wire up getrandom() vDSO implementation (2025-05-23
12:53:18 +0000)
are available in the Git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/alexghiti/linux
tags/riscv-mw3-6.16-rc1
for you to fetch changes up to 0036298021eae09ec93167a5e4721bfe122d828b:
Merge patch series "riscv: misaligned: fix misaligned accesses
handling in put/get_user()" (2025-06-04 11:59:51 +0000)
----------------------------------------------------------------
riscv patches for 6.16-rc1, part 3
* Add SBI FWFT support
----------------------------------------------------------------
Alexandre Ghiti (3):
Merge patch series "riscv: add SBI FWFT misaligned exception
delegation support"
riscv: make unsafe user copy routines use existing assembly routines
Merge patch series "riscv: misaligned: fix misaligned accesses
handling in put/get_user()"
Clément Léger (13):
riscv: sbi: add Firmware Feature (FWFT) SBI extensions definitions
riscv: sbi: remove useless parenthesis
riscv: sbi: add new SBI error mappings
riscv: sbi: add FWFT extension interface
riscv: sbi: add SBI FWFT extension calls
riscv: misaligned: request misaligned exception from SBI
riscv: misaligned: use on_each_cpu() for scalar misaligned access
probing
riscv: misaligned: declare misaligned_access_speed under
CONFIG_RISCV_MISALIGNED
riscv: misaligned: move emulated access uniformity check in a
function
riscv: misaligned: add a function to check misalign trap delegability
selftests: riscv: add misaligned access testing
riscv: process: use unsigned int instead of unsigned long for
put_user()
riscv: uaccess: do not do misaligned accesses in get/put_user()
arch/riscv/include/asm/asm-prototypes.h | 2 +-
arch/riscv/include/asm/cpufeature.h | 14 +-
arch/riscv/include/asm/sbi.h | 60 +++++
arch/riscv/include/asm/uaccess.h | 48 ++--
arch/riscv/kernel/process.c | 2 +-
arch/riscv/kernel/sbi.c | 81 ++++++-
arch/riscv/kernel/traps_misaligned.c | 112 +++++++++-
arch/riscv/kernel/unaligned_access_speed.c | 8 +-
arch/riscv/lib/riscv_v_helpers.c | 11 +-
arch/riscv/lib/uaccess.S | 50 +++--
arch/riscv/lib/uaccess_vector.S | 15 +-
tools/testing/selftests/riscv/Makefile | 2 +-
tools/testing/selftests/riscv/misaligned/.gitignore | 1 +
tools/testing/selftests/riscv/misaligned/Makefile | 12 +
tools/testing/selftests/riscv/misaligned/common.S | 33 +++
tools/testing/selftests/riscv/misaligned/fpu.S | 180 +++++++++++++++
tools/testing/selftests/riscv/misaligned/gp.S | 102 +++++++++
.../testing/selftests/riscv/misaligned/misaligned.c | 253
++++++++++++++++++++++
18 files changed, 917 insertions(+), 69 deletions(-)
create mode 100644 tools/testing/selftests/riscv/misaligned/.gitignore
create mode 100644 tools/testing/selftests/riscv/misaligned/Makefile
create mode 100644 tools/testing/selftests/riscv/misaligned/common.S
create mode 100644 tools/testing/selftests/riscv/misaligned/fpu.S
create mode 100644 tools/testing/selftests/riscv/misaligned/gp.S
create mode 100644 tools/testing/selftests/riscv/misaligned/misaligned.c
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^ permalink raw reply [flat|nested] 2+ messages in thread
* Re: [GIT PULL] RISC-V Patches for the 6.16 Merge Window, Part 3
2025-06-05 7:29 [GIT PULL] RISC-V Patches for the 6.16 Merge Window, Part 3 Alexandre Ghiti
@ 2025-06-05 18:06 ` Palmer Dabbelt
0 siblings, 0 replies; 2+ messages in thread
From: Palmer Dabbelt @ 2025-06-05 18:06 UTC (permalink / raw)
To: Alexandre Ghiti; +Cc: linux-riscv
On Thu, 05 Jun 2025 00:29:32 PDT (-0700), Alexandre Ghiti wrote:
> The following changes since commit dc5240f09bca7b5fc72ad8894d6b9321bce51139:
>
> RISC-V: vDSO: Wire up getrandom() vDSO implementation (2025-05-23
> 12:53:18 +0000)
>
> are available in the Git repository at:
>
> git://git.kernel.org/pub/scm/linux/kernel/git/alexghiti/linux
> tags/riscv-mw3-6.16-rc1
>
> for you to fetch changes up to 0036298021eae09ec93167a5e4721bfe122d828b:
>
> Merge patch series "riscv: misaligned: fix misaligned accesses
> handling in put/get_user()" (2025-06-04 11:59:51 +0000)
I haven't really gotten to this one yet, but something's wrong with the
other two PRs -- I think things are getting rebased somewhere in your
flow, as there's duplicate patches floating around and some of the merge
commits are getting lost.
I'm going to try and fix it...
>
> ----------------------------------------------------------------
> riscv patches for 6.16-rc1, part 3
>
> * Add SBI FWFT support
>
> ----------------------------------------------------------------
> Alexandre Ghiti (3):
> Merge patch series "riscv: add SBI FWFT misaligned exception
> delegation support"
> riscv: make unsafe user copy routines use existing assembly routines
> Merge patch series "riscv: misaligned: fix misaligned accesses
> handling in put/get_user()"
>
> Clément Léger (13):
> riscv: sbi: add Firmware Feature (FWFT) SBI extensions definitions
> riscv: sbi: remove useless parenthesis
> riscv: sbi: add new SBI error mappings
> riscv: sbi: add FWFT extension interface
> riscv: sbi: add SBI FWFT extension calls
> riscv: misaligned: request misaligned exception from SBI
> riscv: misaligned: use on_each_cpu() for scalar misaligned access
> probing
> riscv: misaligned: declare misaligned_access_speed under
> CONFIG_RISCV_MISALIGNED
> riscv: misaligned: move emulated access uniformity check in a
> function
> riscv: misaligned: add a function to check misalign trap delegability
> selftests: riscv: add misaligned access testing
> riscv: process: use unsigned int instead of unsigned long for
> put_user()
> riscv: uaccess: do not do misaligned accesses in get/put_user()
>
> arch/riscv/include/asm/asm-prototypes.h | 2 +-
> arch/riscv/include/asm/cpufeature.h | 14 +-
> arch/riscv/include/asm/sbi.h | 60 +++++
> arch/riscv/include/asm/uaccess.h | 48 ++--
> arch/riscv/kernel/process.c | 2 +-
> arch/riscv/kernel/sbi.c | 81 ++++++-
> arch/riscv/kernel/traps_misaligned.c | 112 +++++++++-
> arch/riscv/kernel/unaligned_access_speed.c | 8 +-
> arch/riscv/lib/riscv_v_helpers.c | 11 +-
> arch/riscv/lib/uaccess.S | 50 +++--
> arch/riscv/lib/uaccess_vector.S | 15 +-
> tools/testing/selftests/riscv/Makefile | 2 +-
> tools/testing/selftests/riscv/misaligned/.gitignore | 1 +
> tools/testing/selftests/riscv/misaligned/Makefile | 12 +
> tools/testing/selftests/riscv/misaligned/common.S | 33 +++
> tools/testing/selftests/riscv/misaligned/fpu.S | 180 +++++++++++++++
> tools/testing/selftests/riscv/misaligned/gp.S | 102 +++++++++
> .../testing/selftests/riscv/misaligned/misaligned.c | 253
> ++++++++++++++++++++++
> 18 files changed, 917 insertions(+), 69 deletions(-)
> create mode 100644 tools/testing/selftests/riscv/misaligned/.gitignore
> create mode 100644 tools/testing/selftests/riscv/misaligned/Makefile
> create mode 100644 tools/testing/selftests/riscv/misaligned/common.S
> create mode 100644 tools/testing/selftests/riscv/misaligned/fpu.S
> create mode 100644 tools/testing/selftests/riscv/misaligned/gp.S
> create mode 100644 tools/testing/selftests/riscv/misaligned/misaligned.c
>
>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
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2025-06-05 7:29 [GIT PULL] RISC-V Patches for the 6.16 Merge Window, Part 3 Alexandre Ghiti
2025-06-05 18:06 ` Palmer Dabbelt
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