From mboxrd@z Thu Jan 1 00:00:00 1970 From: Shawn Lin Subject: [PATCH 1/2] mmc: dw_mmc-rockchip: add default drv phase support Date: Fri, 6 May 2016 17:40:48 +0800 Message-ID: <1462527648-24443-1-git-send-email-shawn.lin@rock-chips.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+glpar-linux-rockchip=m.gmane.org-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org To: Jaehoon Chung Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Ulf Hansson , Heiko Stuebner , Shawn Lin , Brian Norris , linux-mmc-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Doug Anderson , linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, Rob Herring List-Id: linux-rockchip.vger.kernel.org This patch introduces default drv phase exposed to dts for users to set drv phase. If default-drv-phase is not assigned, let's set it to 180 degrees. Signed-off-by: Shawn Lin --- drivers/mmc/host/dw_mmc-rockchip.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/mmc/host/dw_mmc-rockchip.c b/drivers/mmc/host/dw_mmc-rockchip.c index 8c20b81..482eff1 100644 --- a/drivers/mmc/host/dw_mmc-rockchip.c +++ b/drivers/mmc/host/dw_mmc-rockchip.c @@ -24,6 +24,7 @@ struct dw_mci_rockchip_priv_data { struct clk *drv_clk; struct clk *sample_clk; int default_sample_phase; + int default_drv_phase; }; static void dw_mci_rk3288_set_ios(struct dw_mci *host, struct mmc_ios *ios) @@ -66,6 +67,9 @@ static void dw_mci_rk3288_set_ios(struct dw_mci *host, struct mmc_ios *ios) /* Make sure we use phases which we can enumerate with */ if (!IS_ERR(priv->sample_clk)) clk_set_phase(priv->sample_clk, priv->default_sample_phase); + + if (!IS_ERR(priv->drv_clk)) + clk_set_phase(priv->drv_clk, priv->default_drv_phase); } #define NUM_PHASES 360 @@ -203,6 +207,10 @@ static int dw_mci_rk3288_parse_dt(struct dw_mci *host) &priv->default_sample_phase)) priv->default_sample_phase = 0; + if (of_property_read_u32(np, "rockchip,default-drv-phase", + &priv->default_drv_phase)) + priv->default_drv_phase = 180; + priv->drv_clk = devm_clk_get(host->dev, "ciu-drive"); if (IS_ERR(priv->drv_clk)) dev_dbg(host->dev, "ciu_drv not available\n"); -- 2.3.7