From mboxrd@z Thu Jan 1 00:00:00 1970 From: Heiko Stuebner Subject: Re: [PATCH] ARM: dts: rockchip: fix PPI misconfiguration on Cortex-A9 socs Date: Wed, 22 Mar 2017 13:01:30 +0100 Message-ID: <1510641.DEbmyROnA9@phil> References: <20170321231428.23802-1-heiko@sntech.de> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: In-Reply-To: <20170321231428.23802-1-heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+glpar-linux-rockchip=m.gmane.org-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org To: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org List-Id: linux-rockchip.vger.kernel.org Am Mittwoch, 22. M=E4rz 2017, 00:14:28 CET schrieb Heiko Stuebner: > According to [0] pointed out by Marc Zyngier in a report about a > similar error message, PPIs 11 and 13 are edge triggered on > Cortex-A9 socs including the rk3066 and rk3188 which currently > mark them as level triggered. > = > Until some time ago the gic did not care but commit 992345a58e0c > ("irqchip/gic: WARN if setting the interrupt type for a PPI fails") > introduced a warning for that case. > = > Fix the warning on these socs by describing the interrupts correctly > and also using the binding constants for easier reading in the future. > = > [0] http://infocenter.arm.com/help/topic/com.arm.doc.ddi0407f/CCHEIGIC.ht= ml > = > Signed-off-by: Heiko Stuebner applied for 4.12