From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Schultz Subject: [PATCH] ARM: dts: rockchip: Add dp83867 CLK_OUT muxing Date: Mon, 5 Mar 2018 13:45:11 +0100 Message-ID: <1520253911-46218-1-git-send-email-d.schultz@phytec.de> Return-path: Sender: linux-kernel-owner@vger.kernel.org To: heiko@sntech.de, robh+dt@kernel.org, mark.rutland@arm.com, linux@armlinux.org.uk, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: w.egorov@phytec.de List-Id: linux-rockchip.vger.kernel.org The CLK_O_SEL default is synchronous to XI input clock, which is 25 MHz. Set CLK_O_SEL to channel A transmit clock so we have 125 MHz on CLK_OUT. Signed-off-by: Daniel Schultz --- The binding will be added with the next merge of net-next: https://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next.git/commit/?id=9708fb630d19ee51ae3aeb3a533e3010da0e8570 arch/arm/boot/dts/rk3288-phycore-som.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/rk3288-phycore-som.dtsi b/arch/arm/boot/dts/rk3288-phycore-som.dtsi index bdd80aa..e60535d 100644 --- a/arch/arm/boot/dts/rk3288-phycore-som.dtsi +++ b/arch/arm/boot/dts/rk3288-phycore-som.dtsi @@ -141,6 +141,7 @@ ti,tx-internal-delay = ; ti,fifo-depth = ; enet-phy-lane-no-swap; + ti,clk-output-sel = ; }; }; }; -- 2.7.4