From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E64C3C433B4 for ; Tue, 20 Apr 2021 07:35:51 +0000 (UTC) Received: from desiato.infradead.org (desiato.infradead.org [90.155.92.199]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 6CCDC608FE for ; Tue, 20 Apr 2021 07:35:50 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 6CCDC608FE Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=sntech.de Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=desiato.20200630; h=Sender:Content-Transfer-Encoding :Content-Type:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-ID:Date: Subject:Cc:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=+k6OgC+S+TjxXdRkQShL8wuQCaileCeWypkV6tQvmdk=; b=W7wQDIybElKWetoFAbmzjZMyQ zP9Eg7ZGfHdvCl2X9LYDdJs6wSxYKwTUy1+tDKCHOPbL7CJMZ+MKoObjDrteX7wVSyKzq10C7qv9i QhVKqqmGDQW3HJb/xZKI+f6TvVbp7vVn2CnEWvkAwR9TTfxHYjotrvW2dPMjEqpumEX1RJeFCR+g1 4F/GMv9m6PsWjCDyWu6oGPgisI2A1Y5uxAo1aEsfRog7b4wxnSrTjizLlVdQvSUwMAR/p+Ww8N6ee thv74khExaAof/jAqpUbG3mJCDymYp/HcGurtks+ERRl1SrsQJ9eeppl9NI5dFtXAapYfuw+cFXxz kGc+ivDbA==; Received: from localhost ([::1] helo=desiato.infradead.org) by desiato.infradead.org with esmtp (Exim 4.94 #2 (Red Hat Linux)) id 1lYkv9-00BUOR-99; Tue, 20 Apr 2021 07:35:43 +0000 Received: from bombadil.infradead.org ([2607:7c80:54:e::133]) by desiato.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) id 1lYkv6-00BUNc-9p for linux-rockchip@desiato.infradead.org; Tue, 20 Apr 2021 07:35:41 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=bombadil.20210309; h=Content-Type: Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date :Subject:Cc:To:From:Sender:Reply-To:Content-ID:Content-Description; bh=8kHSrawoXUrbjDL1ZC5mfNdDrp0z6Q8wyBLBDxABOr0=; b=gxlKZuJOEVLNgIDV9vvkU7clWz AGq5me72nWEuFmrCXxqD72fgixB2MqXH7HiV74yTsk9ePg7sUoX4+h2o6wCFiHL4ZOY+kSrbVeggu TSqPjde/ipT+AcXhyUm3gfPlx+7U124iwSHDNJpmKc0dBqTKINGrphtslSdJktn9FDSuowa6euu5w ivWYajaq0dyIBkxZ4f/LP+1LLY+U8/bT5yJh4acO/jXGfqhOt43jM+3DydKEQjzfzMhgt9BDWXLgp 2+ccAjtFEIyWYkt1/Uttd+4rQfv/KI5NMdcF79LO+6Z8oZoP4jKqhHC2+ibkltO80AriprTZolUJ1 X7II1rNQ==; Received: from gloria.sntech.de ([185.11.138.130]) by bombadil.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) id 1lYkuz-00BswC-E8 for linux-rockchip@lists.infradead.org; Tue, 20 Apr 2021 07:35:38 +0000 Received: from ip5f5aa64a.dynamic.kabel-deutschland.de ([95.90.166.74] helo=diego.localnet) by gloria.sntech.de with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1lYkuu-0003vQ-EM; Tue, 20 Apr 2021 09:35:28 +0200 From: Heiko =?ISO-8859-1?Q?St=FCbner?= To: linus.walleij@linaro.org, Jianqun Xu Cc: huangtao@rock-chips.com, linux-gpio@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Jianqun Xu Subject: Re: [PATCH] pinctrl: rockchip: do coding style for mux route struct Date: Tue, 20 Apr 2021 09:35:27 +0200 Message-ID: <15909449.hlxOUv9cDv@diego> In-Reply-To: <20210406025356.534876-1-jay.xu@rock-chips.com> References: <20210406025356.534876-1-jay.xu@rock-chips.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210420_003533_840893_0474D06E X-CRM114-Status: GOOD ( 24.35 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org Hi, Am Dienstag, 6. April 2021, 04:53:56 CEST schrieb Jianqun Xu: > The mux route tables take many lines for each SoC, and it will be more > instances for newly SoC, that makes the file size increase larger. > > This patch only do coding style for mux route struct, by adding a new > definition and replace the structs by script which supplied by > huangtao@rock-chips.com > > sed -i -e " > /static struct rockchip_mux_route_data /bcheck > b > :append-next-line > N > :check > /^[^;]*$/bappend-next-line > s/[[:blank:]]*.bank_num = \([[:digit:]]*,\)\n/\tRK_MUXROUTE_SAME(\1/g > s/[[:blank:]]*.pin =[[:blank:]]*0,\n/ RK_PA0,/g > s/[[:blank:]]*.pin =[[:blank:]]*1,\n/ RK_PA1,/g > s/[[:blank:]]*.pin =[[:blank:]]*2,\n/ RK_PA2,/g > s/[[:blank:]]*.pin =[[:blank:]]*3,\n/ RK_PA3,/g > s/[[:blank:]]*.pin =[[:blank:]]*4,\n/ RK_PA4,/g > s/[[:blank:]]*.pin =[[:blank:]]*5,\n/ RK_PA5,/g > s/[[:blank:]]*.pin =[[:blank:]]*6,\n/ RK_PA6,/g > s/[[:blank:]]*.pin =[[:blank:]]*7,\n/ RK_PA7,/g > s/[[:blank:]]*.pin =[[:blank:]]*8,\n/ RK_PB0,/g > s/[[:blank:]]*.pin =[[:blank:]]*9,\n/ RK_PB1,/g > s/[[:blank:]]*.pin =[[:blank:]]*10,\n/ RK_PB2,/g > s/[[:blank:]]*.pin =[[:blank:]]*11,\n/ RK_PB3,/g > s/[[:blank:]]*.pin =[[:blank:]]*12,\n/ RK_PB4,/g > s/[[:blank:]]*.pin =[[:blank:]]*13,\n/ RK_PB5,/g > s/[[:blank:]]*.pin =[[:blank:]]*14,\n/ RK_PB6,/g > s/[[:blank:]]*.pin =[[:blank:]]*15,\n/ RK_PB7,/g > s/[[:blank:]]*.pin =[[:blank:]]*16,\n/ RK_PC0,/g > s/[[:blank:]]*.pin =[[:blank:]]*17,\n/ RK_PC1,/g > s/[[:blank:]]*.pin =[[:blank:]]*18,\n/ RK_PC2,/g > s/[[:blank:]]*.pin =[[:blank:]]*19,\n/ RK_PC3,/g > s/[[:blank:]]*.pin =[[:blank:]]*20,\n/ RK_PC4,/g > s/[[:blank:]]*.pin =[[:blank:]]*21,\n/ RK_PC5,/g > s/[[:blank:]]*.pin =[[:blank:]]*22,\n/ RK_PC6,/g > s/[[:blank:]]*.pin =[[:blank:]]*23,\n/ RK_PC7,/g > s/[[:blank:]]*.pin =[[:blank:]]*24,\n/ RK_PD0,/g > s/[[:blank:]]*.pin =[[:blank:]]*25,\n/ RK_PD1,/g > s/[[:blank:]]*.pin =[[:blank:]]*26,\n/ RK_PD2,/g > s/[[:blank:]]*.pin =[[:blank:]]*27,\n/ RK_PD3,/g > s/[[:blank:]]*.pin =[[:blank:]]*28,\n/ RK_PD4,/g > s/[[:blank:]]*.pin =[[:blank:]]*29,\n/ RK_PD5,/g > s/[[:blank:]]*.pin =[[:blank:]]*30,\n/ RK_PD6,/g > s/[[:blank:]]*.pin =[[:blank:]]*31,\n/ RK_PD7,/g > s/[[:blank:]]*.func = \([[:digit:]]*,\)\n/ \1/g > s/[[:blank:]]*.route_location =[[:blank:]]*\([[:print:]]*,\)\n//g > s/[[:blank:]]*.route_offset = \(0x[[:xdigit:]]*,\)\n/ \1/g > s/[[:blank:]]*.route_val =[[:blank:]]*\([[:print:]]*\),\n/ \1),/g > s/\t{\n//g > s/\t}, {\n//g > s/\t},//g > s/[[:blank:]]*\(\/\*[[:print:]]*\*\/\)\n[[:blank:]]*RK_MUXROUTE_SAME(\([[:print:]]*\)),\n/\tRK_MUXROUTE_SAME(\2), \1\n/g > s/[[:blank:]]*\(\/\*[[:print:]]*\*\/\)\n[[:blank:]]*RK_MUXROUTE_SAME(\([[:print:]]*\)),/\tRK_MUXROUTE_SAME(\2), \1\n/g > " drivers/pinctrl/pinctrl-rockchip.c > > Signed-off-by: Jianqun Xu > Change-Id: Ifc823d9557605b9dfcc9c0455a739f04f3fce5be Change-id should not be in here. Somehow I remember giving this a "reviewed-by" before in some previous version, but my memory may be faulty, so Reviewed-by: Heiko Stuebner and of course I like this change very much ;-) Though it may be really helpful to not send these individual patches but instead make it part of the series and put it at the beginning. Tracking the order patches should get applied when they're sent individually can get very hard. Heiko > --- > drivers/pinctrl/pinctrl-rockchip.c | 669 +++++------------------------ > 1 file changed, 99 insertions(+), 570 deletions(-) > > diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c > index deabfbc74a01..6ba31c66ef8b 100644 > --- a/drivers/pinctrl/pinctrl-rockchip.c > +++ b/drivers/pinctrl/pinctrl-rockchip.c > @@ -292,6 +292,25 @@ struct rockchip_pin_bank { > .pull_type[3] = pull3, \ > } > > +#define PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, FLAG) \ > + { \ > + .bank_num = ID, \ > + .pin = PIN, \ > + .func = FUNC, \ > + .route_offset = REG, \ > + .route_val = VAL, \ > + .route_location = FLAG, \ > + } > + > +#define RK_MUXROUTE_SAME(ID, PIN, FUNC, REG, VAL) \ > + PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_SAME) > + > +#define RK_MUXROUTE_GRF(ID, PIN, FUNC, REG, VAL) \ > + PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_GRF) > + > +#define RK_MUXROUTE_PMU(ID, PIN, FUNC, REG, VAL) \ > + PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_PMU) > + > /** > * struct rockchip_mux_recalced_data: represent a pin iomux data. > * @num: bank number. > @@ -803,597 +822,107 @@ static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin, > } > > static struct rockchip_mux_route_data px30_mux_route_data[] = { > - { > - /* cif-d2m0 */ > - .bank_num = 2, > - .pin = 0, > - .func = 1, > - .route_offset = 0x184, > - .route_val = BIT(16 + 7), > - }, { > - /* cif-d2m1 */ > - .bank_num = 3, > - .pin = 3, > - .func = 3, > - .route_offset = 0x184, > - .route_val = BIT(16 + 7) | BIT(7), > - }, { > - /* pdm-m0 */ > - .bank_num = 3, > - .pin = 22, > - .func = 2, > - .route_offset = 0x184, > - .route_val = BIT(16 + 8), > - }, { > - /* pdm-m1 */ > - .bank_num = 2, > - .pin = 22, > - .func = 1, > - .route_offset = 0x184, > - .route_val = BIT(16 + 8) | BIT(8), > - }, { > - /* uart2-rxm0 */ > - .bank_num = 1, > - .pin = 27, > - .func = 2, > - .route_offset = 0x184, > - .route_val = BIT(16 + 10), > - }, { > - /* uart2-rxm1 */ > - .bank_num = 2, > - .pin = 14, > - .func = 2, > - .route_offset = 0x184, > - .route_val = BIT(16 + 10) | BIT(10), > - }, { > - /* uart3-rxm0 */ > - .bank_num = 0, > - .pin = 17, > - .func = 2, > - .route_offset = 0x184, > - .route_val = BIT(16 + 9), > - }, { > - /* uart3-rxm1 */ > - .bank_num = 1, > - .pin = 15, > - .func = 2, > - .route_offset = 0x184, > - .route_val = BIT(16 + 9) | BIT(9), > - }, > + RK_MUXROUTE_SAME(2, RK_PA0, 1, 0x184, BIT(16 + 7)), /* cif-d2m0 */ > + RK_MUXROUTE_SAME(3, RK_PA3, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d2m1 */ > + RK_MUXROUTE_SAME(3, RK_PC6, 2, 0x184, BIT(16 + 8)), /* pdm-m0 */ > + RK_MUXROUTE_SAME(2, RK_PC6, 1, 0x184, BIT(16 + 8) | BIT(8)), /* pdm-m1 */ > + RK_MUXROUTE_SAME(1, RK_PD3, 2, 0x184, BIT(16 + 10)), /* uart2-rxm0 */ > + RK_MUXROUTE_SAME(2, RK_PB6, 2, 0x184, BIT(16 + 10) | BIT(10)), /* uart2-rxm1 */ > + RK_MUXROUTE_SAME(0, RK_PC1, 2, 0x184, BIT(16 + 9)), /* uart3-rxm0 */ > + RK_MUXROUTE_SAME(1, RK_PB7, 2, 0x184, BIT(16 + 9) | BIT(9)), /* uart3-rxm1 */ > }; > > static struct rockchip_mux_route_data rk3128_mux_route_data[] = { > - { > - /* spi-0 */ > - .bank_num = 1, > - .pin = 10, > - .func = 1, > - .route_offset = 0x144, > - .route_val = BIT(16 + 3) | BIT(16 + 4), > - }, { > - /* spi-1 */ > - .bank_num = 1, > - .pin = 27, > - .func = 3, > - .route_offset = 0x144, > - .route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(3), > - }, { > - /* spi-2 */ > - .bank_num = 0, > - .pin = 13, > - .func = 2, > - .route_offset = 0x144, > - .route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(4), > - }, { > - /* i2s-0 */ > - .bank_num = 1, > - .pin = 5, > - .func = 1, > - .route_offset = 0x144, > - .route_val = BIT(16 + 5), > - }, { > - /* i2s-1 */ > - .bank_num = 0, > - .pin = 14, > - .func = 1, > - .route_offset = 0x144, > - .route_val = BIT(16 + 5) | BIT(5), > - }, { > - /* emmc-0 */ > - .bank_num = 1, > - .pin = 22, > - .func = 2, > - .route_offset = 0x144, > - .route_val = BIT(16 + 6), > - }, { > - /* emmc-1 */ > - .bank_num = 2, > - .pin = 4, > - .func = 2, > - .route_offset = 0x144, > - .route_val = BIT(16 + 6) | BIT(6), > - }, > + RK_MUXROUTE_SAME(1, RK_PB2, 1, 0x144, BIT(16 + 3) | BIT(16 + 4)), /* spi-0 */ > + RK_MUXROUTE_SAME(1, RK_PD3, 3, 0x144, BIT(16 + 3) | BIT(16 + 4) | BIT(3)), /* spi-1 */ > + RK_MUXROUTE_SAME(0, RK_PB5, 2, 0x144, BIT(16 + 3) | BIT(16 + 4) | BIT(4)), /* spi-2 */ > + RK_MUXROUTE_SAME(1, RK_PA5, 1, 0x144, BIT(16 + 5)), /* i2s-0 */ > + RK_MUXROUTE_SAME(0, RK_PB6, 1, 0x144, BIT(16 + 5) | BIT(5)), /* i2s-1 */ > + RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x144, BIT(16 + 6)), /* emmc-0 */ > + RK_MUXROUTE_SAME(2, RK_PA4, 2, 0x144, BIT(16 + 6) | BIT(6)), /* emmc-1 */ > }; > > static struct rockchip_mux_route_data rk3188_mux_route_data[] = { > - { > - /* non-iomuxed emmc/flash pins on flash-dqs */ > - .bank_num = 0, > - .pin = 24, > - .func = 1, > - .route_location = ROCKCHIP_ROUTE_GRF, > - .route_offset = 0xa0, > - .route_val = BIT(16 + 11), > - }, { > - /* non-iomuxed emmc/flash pins on emmc-clk */ > - .bank_num = 0, > - .pin = 24, > - .func = 2, > - .route_location = ROCKCHIP_ROUTE_GRF, > - .route_offset = 0xa0, > - .route_val = BIT(16 + 11) | BIT(11), > - }, > + RK_MUXROUTE_SAME(0, RK_PD0, 1, 0xa0, BIT(16 + 11)), /* non-iomuxed emmc/flash pins on flash-dqs */ > + RK_MUXROUTE_SAME(0, RK_PD0, 2, 0xa0, BIT(16 + 11) | BIT(11)), /* non-iomuxed emmc/flash pins on emmc-clk */ > }; > > static struct rockchip_mux_route_data rk3228_mux_route_data[] = { > - { > - /* pwm0-0 */ > - .bank_num = 0, > - .pin = 26, > - .func = 1, > - .route_offset = 0x50, > - .route_val = BIT(16), > - }, { > - /* pwm0-1 */ > - .bank_num = 3, > - .pin = 21, > - .func = 1, > - .route_offset = 0x50, > - .route_val = BIT(16) | BIT(0), > - }, { > - /* pwm1-0 */ > - .bank_num = 0, > - .pin = 27, > - .func = 1, > - .route_offset = 0x50, > - .route_val = BIT(16 + 1), > - }, { > - /* pwm1-1 */ > - .bank_num = 0, > - .pin = 30, > - .func = 2, > - .route_offset = 0x50, > - .route_val = BIT(16 + 1) | BIT(1), > - }, { > - /* pwm2-0 */ > - .bank_num = 0, > - .pin = 28, > - .func = 1, > - .route_offset = 0x50, > - .route_val = BIT(16 + 2), > - }, { > - /* pwm2-1 */ > - .bank_num = 1, > - .pin = 12, > - .func = 2, > - .route_offset = 0x50, > - .route_val = BIT(16 + 2) | BIT(2), > - }, { > - /* pwm3-0 */ > - .bank_num = 3, > - .pin = 26, > - .func = 1, > - .route_offset = 0x50, > - .route_val = BIT(16 + 3), > - }, { > - /* pwm3-1 */ > - .bank_num = 1, > - .pin = 11, > - .func = 2, > - .route_offset = 0x50, > - .route_val = BIT(16 + 3) | BIT(3), > - }, { > - /* sdio-0_d0 */ > - .bank_num = 1, > - .pin = 1, > - .func = 1, > - .route_offset = 0x50, > - .route_val = BIT(16 + 4), > - }, { > - /* sdio-1_d0 */ > - .bank_num = 3, > - .pin = 2, > - .func = 1, > - .route_offset = 0x50, > - .route_val = BIT(16 + 4) | BIT(4), > - }, { > - /* spi-0_rx */ > - .bank_num = 0, > - .pin = 13, > - .func = 2, > - .route_offset = 0x50, > - .route_val = BIT(16 + 5), > - }, { > - /* spi-1_rx */ > - .bank_num = 2, > - .pin = 0, > - .func = 2, > - .route_offset = 0x50, > - .route_val = BIT(16 + 5) | BIT(5), > - }, { > - /* emmc-0_cmd */ > - .bank_num = 1, > - .pin = 22, > - .func = 2, > - .route_offset = 0x50, > - .route_val = BIT(16 + 7), > - }, { > - /* emmc-1_cmd */ > - .bank_num = 2, > - .pin = 4, > - .func = 2, > - .route_offset = 0x50, > - .route_val = BIT(16 + 7) | BIT(7), > - }, { > - /* uart2-0_rx */ > - .bank_num = 1, > - .pin = 19, > - .func = 2, > - .route_offset = 0x50, > - .route_val = BIT(16 + 8), > - }, { > - /* uart2-1_rx */ > - .bank_num = 1, > - .pin = 10, > - .func = 2, > - .route_offset = 0x50, > - .route_val = BIT(16 + 8) | BIT(8), > - }, { > - /* uart1-0_rx */ > - .bank_num = 1, > - .pin = 10, > - .func = 1, > - .route_offset = 0x50, > - .route_val = BIT(16 + 11), > - }, { > - /* uart1-1_rx */ > - .bank_num = 3, > - .pin = 13, > - .func = 1, > - .route_offset = 0x50, > - .route_val = BIT(16 + 11) | BIT(11), > - }, > + RK_MUXROUTE_SAME(0, RK_PD2, 1, 0x50, BIT(16)), /* pwm0-0 */ > + RK_MUXROUTE_SAME(3, RK_PC5, 1, 0x50, BIT(16) | BIT(0)), /* pwm0-1 */ > + RK_MUXROUTE_SAME(0, RK_PD3, 1, 0x50, BIT(16 + 1)), /* pwm1-0 */ > + RK_MUXROUTE_SAME(0, RK_PD6, 2, 0x50, BIT(16 + 1) | BIT(1)), /* pwm1-1 */ > + RK_MUXROUTE_SAME(0, RK_PD4, 1, 0x50, BIT(16 + 2)), /* pwm2-0 */ > + RK_MUXROUTE_SAME(1, RK_PB4, 2, 0x50, BIT(16 + 2) | BIT(2)), /* pwm2-1 */ > + RK_MUXROUTE_SAME(3, RK_PD2, 1, 0x50, BIT(16 + 3)), /* pwm3-0 */ > + RK_MUXROUTE_SAME(1, RK_PB3, 2, 0x50, BIT(16 + 3) | BIT(3)), /* pwm3-1 */ > + RK_MUXROUTE_SAME(1, RK_PA1, 1, 0x50, BIT(16 + 4)), /* sdio-0_d0 */ > + RK_MUXROUTE_SAME(3, RK_PA2, 1, 0x50, BIT(16 + 4) | BIT(4)), /* sdio-1_d0 */ > + RK_MUXROUTE_SAME(0, RK_PB5, 2, 0x50, BIT(16 + 5)), /* spi-0_rx */ > + RK_MUXROUTE_SAME(2, RK_PA0, 2, 0x50, BIT(16 + 5) | BIT(5)), /* spi-1_rx */ > + RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x50, BIT(16 + 7)), /* emmc-0_cmd */ > + RK_MUXROUTE_SAME(2, RK_PA4, 2, 0x50, BIT(16 + 7) | BIT(7)), /* emmc-1_cmd */ > + RK_MUXROUTE_SAME(1, RK_PC3, 2, 0x50, BIT(16 + 8)), /* uart2-0_rx */ > + RK_MUXROUTE_SAME(1, RK_PB2, 2, 0x50, BIT(16 + 8) | BIT(8)), /* uart2-1_rx */ > + RK_MUXROUTE_SAME(1, RK_PB2, 1, 0x50, BIT(16 + 11)), /* uart1-0_rx */ > + RK_MUXROUTE_SAME(3, RK_PB5, 1, 0x50, BIT(16 + 11) | BIT(11)), /* uart1-1_rx */ > }; > > static struct rockchip_mux_route_data rk3288_mux_route_data[] = { > - { > - /* edphdmi_cecinoutt1 */ > - .bank_num = 7, > - .pin = 16, > - .func = 2, > - .route_offset = 0x264, > - .route_val = BIT(16 + 12) | BIT(12), > - }, { > - /* edphdmi_cecinout */ > - .bank_num = 7, > - .pin = 23, > - .func = 4, > - .route_offset = 0x264, > - .route_val = BIT(16 + 12), > - }, > + RK_MUXROUTE_SAME(7, RK_PC0, 2, 0x264, BIT(16 + 12) | BIT(12)), /* edphdmi_cecinoutt1 */ > + RK_MUXROUTE_SAME(7, RK_PC7, 4, 0x264, BIT(16 + 12)), /* edphdmi_cecinout */ > }; > > static struct rockchip_mux_route_data rk3308_mux_route_data[] = { > - { > - /* rtc_clk */ > - .bank_num = 0, > - .pin = 19, > - .func = 1, > - .route_offset = 0x314, > - .route_val = BIT(16 + 0) | BIT(0), > - }, { > - /* uart2_rxm0 */ > - .bank_num = 1, > - .pin = 22, > - .func = 2, > - .route_offset = 0x314, > - .route_val = BIT(16 + 2) | BIT(16 + 3), > - }, { > - /* uart2_rxm1 */ > - .bank_num = 4, > - .pin = 26, > - .func = 2, > - .route_offset = 0x314, > - .route_val = BIT(16 + 2) | BIT(16 + 3) | BIT(2), > - }, { > - /* i2c3_sdam0 */ > - .bank_num = 0, > - .pin = 15, > - .func = 2, > - .route_offset = 0x608, > - .route_val = BIT(16 + 8) | BIT(16 + 9), > - }, { > - /* i2c3_sdam1 */ > - .bank_num = 3, > - .pin = 12, > - .func = 2, > - .route_offset = 0x608, > - .route_val = BIT(16 + 8) | BIT(16 + 9) | BIT(8), > - }, { > - /* i2c3_sdam2 */ > - .bank_num = 2, > - .pin = 0, > - .func = 3, > - .route_offset = 0x608, > - .route_val = BIT(16 + 8) | BIT(16 + 9) | BIT(9), > - }, { > - /* i2s-8ch-1-sclktxm0 */ > - .bank_num = 1, > - .pin = 3, > - .func = 2, > - .route_offset = 0x308, > - .route_val = BIT(16 + 3), > - }, { > - /* i2s-8ch-1-sclkrxm0 */ > - .bank_num = 1, > - .pin = 4, > - .func = 2, > - .route_offset = 0x308, > - .route_val = BIT(16 + 3), > - }, { > - /* i2s-8ch-1-sclktxm1 */ > - .bank_num = 1, > - .pin = 13, > - .func = 2, > - .route_offset = 0x308, > - .route_val = BIT(16 + 3) | BIT(3), > - }, { > - /* i2s-8ch-1-sclkrxm1 */ > - .bank_num = 1, > - .pin = 14, > - .func = 2, > - .route_offset = 0x308, > - .route_val = BIT(16 + 3) | BIT(3), > - }, { > - /* pdm-clkm0 */ > - .bank_num = 1, > - .pin = 4, > - .func = 3, > - .route_offset = 0x308, > - .route_val = BIT(16 + 12) | BIT(16 + 13), > - }, { > - /* pdm-clkm1 */ > - .bank_num = 1, > - .pin = 14, > - .func = 4, > - .route_offset = 0x308, > - .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(12), > - }, { > - /* pdm-clkm2 */ > - .bank_num = 2, > - .pin = 6, > - .func = 2, > - .route_offset = 0x308, > - .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(13), > - }, { > - /* pdm-clkm-m2 */ > - .bank_num = 2, > - .pin = 4, > - .func = 3, > - .route_offset = 0x600, > - .route_val = BIT(16 + 2) | BIT(2), > - }, { > - /* spi1_miso */ > - .bank_num = 3, > - .pin = 10, > - .func = 3, > - .route_offset = 0x314, > - .route_val = BIT(16 + 9), > - }, { > - /* spi1_miso_m1 */ > - .bank_num = 2, > - .pin = 4, > - .func = 2, > - .route_offset = 0x314, > - .route_val = BIT(16 + 9) | BIT(9), > - }, { > - /* owire_m0 */ > - .bank_num = 0, > - .pin = 11, > - .func = 3, > - .route_offset = 0x314, > - .route_val = BIT(16 + 10) | BIT(16 + 11), > - }, { > - /* owire_m1 */ > - .bank_num = 1, > - .pin = 22, > - .func = 7, > - .route_offset = 0x314, > - .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(10), > - }, { > - /* owire_m2 */ > - .bank_num = 2, > - .pin = 2, > - .func = 5, > - .route_offset = 0x314, > - .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(11), > - }, { > - /* can_rxd_m0 */ > - .bank_num = 0, > - .pin = 11, > - .func = 2, > - .route_offset = 0x314, > - .route_val = BIT(16 + 12) | BIT(16 + 13), > - }, { > - /* can_rxd_m1 */ > - .bank_num = 1, > - .pin = 22, > - .func = 5, > - .route_offset = 0x314, > - .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(12), > - }, { > - /* can_rxd_m2 */ > - .bank_num = 2, > - .pin = 2, > - .func = 4, > - .route_offset = 0x314, > - .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(13), > - }, { > - /* mac_rxd0_m0 */ > - .bank_num = 1, > - .pin = 20, > - .func = 3, > - .route_offset = 0x314, > - .route_val = BIT(16 + 14), > - }, { > - /* mac_rxd0_m1 */ > - .bank_num = 4, > - .pin = 2, > - .func = 2, > - .route_offset = 0x314, > - .route_val = BIT(16 + 14) | BIT(14), > - }, { > - /* uart3_rx */ > - .bank_num = 3, > - .pin = 12, > - .func = 4, > - .route_offset = 0x314, > - .route_val = BIT(16 + 15), > - }, { > - /* uart3_rx_m1 */ > - .bank_num = 0, > - .pin = 17, > - .func = 3, > - .route_offset = 0x314, > - .route_val = BIT(16 + 15) | BIT(15), > - }, > + RK_MUXROUTE_SAME(0, RK_PC3, 1, 0x314, BIT(16 + 0) | BIT(0)), /* rtc_clk */ > + RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x314, BIT(16 + 2) | BIT(16 + 3)), /* uart2_rxm0 */ > + RK_MUXROUTE_SAME(4, RK_PD2, 2, 0x314, BIT(16 + 2) | BIT(16 + 3) | BIT(2)), /* uart2_rxm1 */ > + RK_MUXROUTE_SAME(0, RK_PB7, 2, 0x608, BIT(16 + 8) | BIT(16 + 9)), /* i2c3_sdam0 */ > + RK_MUXROUTE_SAME(3, RK_PB4, 2, 0x608, BIT(16 + 8) | BIT(16 + 9) | BIT(8)), /* i2c3_sdam1 */ > + RK_MUXROUTE_SAME(2, RK_PA0, 3, 0x608, BIT(16 + 8) | BIT(16 + 9) | BIT(9)), /* i2c3_sdam2 */ > + RK_MUXROUTE_SAME(1, RK_PA3, 2, 0x308, BIT(16 + 3)), /* i2s-8ch-1-sclktxm0 */ > + RK_MUXROUTE_SAME(1, RK_PA4, 2, 0x308, BIT(16 + 3)), /* i2s-8ch-1-sclkrxm0 */ > + RK_MUXROUTE_SAME(1, RK_PB5, 2, 0x308, BIT(16 + 3) | BIT(3)), /* i2s-8ch-1-sclktxm1 */ > + RK_MUXROUTE_SAME(1, RK_PB6, 2, 0x308, BIT(16 + 3) | BIT(3)), /* i2s-8ch-1-sclkrxm1 */ > + RK_MUXROUTE_SAME(1, RK_PA4, 3, 0x308, BIT(16 + 12) | BIT(16 + 13)), /* pdm-clkm0 */ > + RK_MUXROUTE_SAME(1, RK_PB6, 4, 0x308, BIT(16 + 12) | BIT(16 + 13) | BIT(12)), /* pdm-clkm1 */ > + RK_MUXROUTE_SAME(2, RK_PA6, 2, 0x308, BIT(16 + 12) | BIT(16 + 13) | BIT(13)), /* pdm-clkm2 */ > + RK_MUXROUTE_SAME(2, RK_PA4, 3, 0x600, BIT(16 + 2) | BIT(2)), /* pdm-clkm-m2 */ > + RK_MUXROUTE_SAME(3, RK_PB2, 3, 0x314, BIT(16 + 9)), /* spi1_miso */ > + RK_MUXROUTE_SAME(2, RK_PA4, 2, 0x314, BIT(16 + 9) | BIT(9)), /* spi1_miso_m1 */ > + RK_MUXROUTE_SAME(0, RK_PB3, 3, 0x314, BIT(16 + 10) | BIT(16 + 11)), /* owire_m0 */ > + RK_MUXROUTE_SAME(1, RK_PC6, 7, 0x314, BIT(16 + 10) | BIT(16 + 11) | BIT(10)), /* owire_m1 */ > + RK_MUXROUTE_SAME(2, RK_PA2, 5, 0x314, BIT(16 + 10) | BIT(16 + 11) | BIT(11)), /* owire_m2 */ > + RK_MUXROUTE_SAME(0, RK_PB3, 2, 0x314, BIT(16 + 12) | BIT(16 + 13)), /* can_rxd_m0 */ > + RK_MUXROUTE_SAME(1, RK_PC6, 5, 0x314, BIT(16 + 12) | BIT(16 + 13) | BIT(12)), /* can_rxd_m1 */ > + RK_MUXROUTE_SAME(2, RK_PA2, 4, 0x314, BIT(16 + 12) | BIT(16 + 13) | BIT(13)), /* can_rxd_m2 */ > + RK_MUXROUTE_SAME(1, RK_PC4, 3, 0x314, BIT(16 + 14)), /* mac_rxd0_m0 */ > + RK_MUXROUTE_SAME(4, RK_PA2, 2, 0x314, BIT(16 + 14) | BIT(14)), /* mac_rxd0_m1 */ > + RK_MUXROUTE_SAME(3, RK_PB4, 4, 0x314, BIT(16 + 15)), /* uart3_rx */ > + RK_MUXROUTE_SAME(0, RK_PC1, 3, 0x314, BIT(16 + 15) | BIT(15)), /* uart3_rx_m1 */ > }; > > static struct rockchip_mux_route_data rk3328_mux_route_data[] = { > - { > - /* uart2dbg_rxm0 */ > - .bank_num = 1, > - .pin = 1, > - .func = 2, > - .route_offset = 0x50, > - .route_val = BIT(16) | BIT(16 + 1), > - }, { > - /* uart2dbg_rxm1 */ > - .bank_num = 2, > - .pin = 1, > - .func = 1, > - .route_offset = 0x50, > - .route_val = BIT(16) | BIT(16 + 1) | BIT(0), > - }, { > - /* gmac-m1_rxd0 */ > - .bank_num = 1, > - .pin = 11, > - .func = 2, > - .route_offset = 0x50, > - .route_val = BIT(16 + 2) | BIT(2), > - }, { > - /* gmac-m1-optimized_rxd3 */ > - .bank_num = 1, > - .pin = 14, > - .func = 2, > - .route_offset = 0x50, > - .route_val = BIT(16 + 10) | BIT(10), > - }, { > - /* pdm_sdi0m0 */ > - .bank_num = 2, > - .pin = 19, > - .func = 2, > - .route_offset = 0x50, > - .route_val = BIT(16 + 3), > - }, { > - /* pdm_sdi0m1 */ > - .bank_num = 1, > - .pin = 23, > - .func = 3, > - .route_offset = 0x50, > - .route_val = BIT(16 + 3) | BIT(3), > - }, { > - /* spi_rxdm2 */ > - .bank_num = 3, > - .pin = 2, > - .func = 4, > - .route_offset = 0x50, > - .route_val = BIT(16 + 4) | BIT(16 + 5) | BIT(5), > - }, { > - /* i2s2_sdim0 */ > - .bank_num = 1, > - .pin = 24, > - .func = 1, > - .route_offset = 0x50, > - .route_val = BIT(16 + 6), > - }, { > - /* i2s2_sdim1 */ > - .bank_num = 3, > - .pin = 2, > - .func = 6, > - .route_offset = 0x50, > - .route_val = BIT(16 + 6) | BIT(6), > - }, { > - /* card_iom1 */ > - .bank_num = 2, > - .pin = 22, > - .func = 3, > - .route_offset = 0x50, > - .route_val = BIT(16 + 7) | BIT(7), > - }, { > - /* tsp_d5m1 */ > - .bank_num = 2, > - .pin = 16, > - .func = 3, > - .route_offset = 0x50, > - .route_val = BIT(16 + 8) | BIT(8), > - }, { > - /* cif_data5m1 */ > - .bank_num = 2, > - .pin = 16, > - .func = 4, > - .route_offset = 0x50, > - .route_val = BIT(16 + 9) | BIT(9), > - }, > + RK_MUXROUTE_SAME(1, RK_PA1, 2, 0x50, BIT(16) | BIT(16 + 1)), /* uart2dbg_rxm0 */ > + RK_MUXROUTE_SAME(2, RK_PA1, 1, 0x50, BIT(16) | BIT(16 + 1) | BIT(0)), /* uart2dbg_rxm1 */ > + RK_MUXROUTE_SAME(1, RK_PB3, 2, 0x50, BIT(16 + 2) | BIT(2)), /* gmac-m1_rxd0 */ > + RK_MUXROUTE_SAME(1, RK_PB6, 2, 0x50, BIT(16 + 10) | BIT(10)), /* gmac-m1-optimized_rxd3 */ > + RK_MUXROUTE_SAME(2, RK_PC3, 2, 0x50, BIT(16 + 3)), /* pdm_sdi0m0 */ > + RK_MUXROUTE_SAME(1, RK_PC7, 3, 0x50, BIT(16 + 3) | BIT(3)), /* pdm_sdi0m1 */ > + RK_MUXROUTE_SAME(3, RK_PA2, 4, 0x50, BIT(16 + 4) | BIT(16 + 5) | BIT(5)), /* spi_rxdm2 */ > + RK_MUXROUTE_SAME(1, RK_PD0, 1, 0x50, BIT(16 + 6)), /* i2s2_sdim0 */ > + RK_MUXROUTE_SAME(3, RK_PA2, 6, 0x50, BIT(16 + 6) | BIT(6)), /* i2s2_sdim1 */ > + RK_MUXROUTE_SAME(2, RK_PC6, 3, 0x50, BIT(16 + 7) | BIT(7)), /* card_iom1 */ > + RK_MUXROUTE_SAME(2, RK_PC0, 3, 0x50, BIT(16 + 8) | BIT(8)), /* tsp_d5m1 */ > + RK_MUXROUTE_SAME(2, RK_PC0, 4, 0x50, BIT(16 + 9) | BIT(9)), /* cif_data5m1 */ > }; > > static struct rockchip_mux_route_data rk3399_mux_route_data[] = { > - { > - /* uart2dbga_rx */ > - .bank_num = 4, > - .pin = 8, > - .func = 2, > - .route_offset = 0xe21c, > - .route_val = BIT(16 + 10) | BIT(16 + 11), > - }, { > - /* uart2dbgb_rx */ > - .bank_num = 4, > - .pin = 16, > - .func = 2, > - .route_offset = 0xe21c, > - .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(10), > - }, { > - /* uart2dbgc_rx */ > - .bank_num = 4, > - .pin = 19, > - .func = 1, > - .route_offset = 0xe21c, > - .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(11), > - }, { > - /* pcie_clkreqn */ > - .bank_num = 2, > - .pin = 26, > - .func = 2, > - .route_offset = 0xe21c, > - .route_val = BIT(16 + 14), > - }, { > - /* pcie_clkreqnb */ > - .bank_num = 4, > - .pin = 24, > - .func = 1, > - .route_offset = 0xe21c, > - .route_val = BIT(16 + 14) | BIT(14), > - }, > + RK_MUXROUTE_SAME(4, RK_PB0, 2, 0xe21c, BIT(16 + 10) | BIT(16 + 11)), /* uart2dbga_rx */ > + RK_MUXROUTE_SAME(4, RK_PC0, 2, 0xe21c, BIT(16 + 10) | BIT(16 + 11) | BIT(10)), /* uart2dbgb_rx */ > + RK_MUXROUTE_SAME(4, RK_PC3, 1, 0xe21c, BIT(16 + 10) | BIT(16 + 11) | BIT(11)), /* uart2dbgc_rx */ > + RK_MUXROUTE_SAME(2, RK_PD2, 2, 0xe21c, BIT(16 + 14)), /* pcie_clkreqn */ > + RK_MUXROUTE_SAME(4, RK_PD0, 1, 0xe21c, BIT(16 + 14) | BIT(14)), /* pcie_clkreqnb */ > }; > > static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin, > _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip