[PATCH] ARM: dts: rockchip: explicitly set vcc_sd0 pin to gpio on rk3188-radxarock

[PATCH] ARM: dts: rockchip: explicitly set vcc_sd0 pin to gpio on rk3188-radxarock

[Heiko Stuebner]

It is good practice to make the setting of gpio-pinctrls explicitly in the
devicetree, and in this case even necessary.
Rockchip boards start with iomux settings set to gpio for most pins and
while the linux pinctrl driver also implicitly sets the gpio function if
a pin is requested as gpio that is not necessarily true for other drivers.

The issue in question stems from uboot, where the sdmmc_pwr pin is set
to function 1 (sdmmc-power) by the bootrom when reading the 1st-stage
loader. The regulator controlled by the pin is active-low though, so
when the dwmmc hw-block sets its enabled bit, it actually disables the
regulator. By changing the pin back to gpio we fix that behaviour.

Signed-off-by: Heiko Stuebner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org>
---
 arch/arm/boot/dts/rk3188-radxarock.dts | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/boot/dts/rk3188-radxarock.dts b/arch/arm/boot/dts/rk3188-radxarock.dts
index 51379f36343f..0e5e4cf3d84c 100644
--- a/arch/arm/boot/dts/rk3188-radxarock.dts
+++ b/arch/arm/boot/dts/rk3188-radxarock.dts
@@ -108,6 +108,8 @@
 		regulator-min-microvolt = <3300000>;
 		regulator-max-microvolt = <3300000>;
 		gpio = <&gpio3 RK_PA1 GPIO_ACTIVE_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&sdmmc_pwr>;
 		startup-delay-us = <100000>;
 		vin-supply = <&vcc_io>;
 	};
@@ -371,6 +373,12 @@
 		};
 	};
 
+	sd0 {
+		sdmmc_pwr: sdmmc-pwr {
+			rockchip,pins = <RK_GPIO3 1 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
 	usb {
 		host_vbus_drv: host-vbus-drv {
 			rockchip,pins = <0 3 RK_FUNC_GPIO &pcfg_pull_none>;
-- 
2.18.0

Re: [PATCH] ARM: dts: rockchip: explicitly set vcc_sd0 pin to gpio on rk3188-radxarock

[Heiko Stuebner]

Am Freitag, 21. September 2018, 10:13:41 CEST schrieb Heiko Stuebner:
> It is good practice to make the setting of gpio-pinctrls explicitly in the
> devicetree, and in this case even necessary.
> Rockchip boards start with iomux settings set to gpio for most pins and
> while the linux pinctrl driver also implicitly sets the gpio function if
> a pin is requested as gpio that is not necessarily true for other drivers.
> 
> The issue in question stems from uboot, where the sdmmc_pwr pin is set
> to function 1 (sdmmc-power) by the bootrom when reading the 1st-stage
> loader. The regulator controlled by the pin is active-low though, so
> when the dwmmc hw-block sets its enabled bit, it actually disables the
> regulator. By changing the pin back to gpio we fix that behaviour.
> 
> Signed-off-by: Heiko Stuebner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org>

applied for 4.20