From: Manivannan Sadhasivam <mani@kernel.org>
To: "Lorenzo Pieralisi" <lpieralisi@kernel.org>,
"Krzysztof Wilczyński" <kwilczynski@kernel.org>,
"Rob Herring" <robh@kernel.org>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Heiko Stuebner" <heiko@sntech.de>,
"Niklas Cassel" <cassel@kernel.org>
Cc: Wilfred Mallawa <wilfred.mallawa@wdc.com>,
linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-rockchip@lists.infradead.org
Subject: Re: [PATCH v2] PCI: dw-rockchip: Delay link training after hot reset in EP mode
Date: Fri, 13 Jun 2025 16:52:43 +0530 [thread overview]
Message-ID: <174981376322.39040.626028156798612367.b4-ty@kernel.org> (raw)
In-Reply-To: <20250613101908.2182053-2-cassel@kernel.org>
On Fri, 13 Jun 2025 12:19:09 +0200, Niklas Cassel wrote:
> RK3588 TRM, section "11.6.1.3.3 Hot Reset and Link-Down Reset" states that:
> """
> If you want to delay link re-establishment (after reset) so that you can
> reprogram some registers through DBI, you must set app_ltssm_enable =0
> immediately after core_rst_n as shown in above. This can be achieved by
> enable the app_dly2_en, and end-up the delay by assert app_dly2_done.
> """
>
> [...]
Applied, thanks!
[1/1] PCI: dw-rockchip: Delay link training after hot reset in EP mode
commit: dcca6051a220484f0c1a5cb018f3012735067254
Best regards,
--
Manivannan Sadhasivam <mani@kernel.org>
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
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next prev parent reply other threads:[~2025-06-13 11:32 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-13 10:19 [PATCH v2] PCI: dw-rockchip: Delay link training after hot reset in EP mode Niklas Cassel
2025-06-13 11:22 ` Manivannan Sadhasivam [this message]
2025-06-17 22:01 ` Bjorn Helgaas
2025-06-17 22:05 ` Bjorn Helgaas
2025-06-18 14:23 ` Niklas Cassel
2025-06-18 14:40 ` Niklas Cassel
2025-06-18 19:54 ` Bjorn Helgaas
2025-06-18 14:04 ` Niklas Cassel
2025-06-18 19:59 ` Bjorn Helgaas
2025-06-19 9:53 ` Niklas Cassel
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