[PATCH v2 0/5] Improve Rockchip VOP2 display modes handling on RK3588 HDMI0

Cristian Ciocaltea
2024-12-11T10:18:14Z

VOP2 support for RK3588 SoC is currently not capable to handle the full
range of display modes advertised by the connected screens, e.g. it
doesn't cope well with non-integer refresh rates like 59.94, 29.97,
23.98, etc.

There are two HDMI PHYs available on RK3588, each providing a PLL that
can be used by three out of the four VOP2 video ports as an alternative
and more accurate pixel clock source. This is able to correctly handle
all display modes up to 4K@60Hz.

As for the moment HDMI1 output is not supported upstream, the patch
series targets HDMI0 only.

Additionally, note that testing any HDMI 2.0 specific modes, e.g.
4K@60Hz, requires high TMDS clock ratio and scrambling support [1]. The
patch is usable but not yet ready to be submitted - I will handle this
soon.

Thanks,
Cristian

[1] https://gitlab.collabora.com/hardware-enablement/rockchip-3588/linux/-/commits/rk3588-hdmi-bridge-next-20241115

Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
---
Changes in v2:
- Collected Acked-by tag from Rob and Tested-by from Naoki
- Rebased series onto v6.13-rc1
- Link to v1: https://lore.kernel.org/r/20241116-vop2-hdmi0-disp-modes-v1-0-2bca51db4898@collabora.com

---
Cristian Ciocaltea (5):
dt-bindings: display: vop2: Add optional PLL clock properties
drm/rockchip: vop2: Drop unnecessary if_pixclk_rate computation
drm/rockchip: vop2: Improve display modes handling on RK3588 HDMI0
arm64: dts: rockchip: Enable HDMI0 PHY clk provider on RK3588
arm64: dts: rockchip: Add HDMI0 PHY PLL clock source to VOP2 on RK3588

.../bindings/display/rockchip/rockchip-vop2.yaml | 4 +++
arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 7 +++--
drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 36 +++++++++++++++++++++-
3 files changed, 44 insertions(+), 3 deletions(-)
---
base-commit: 40384c840ea1944d7c5a392e8975ed088ecf0b37
change-id: 20241116-vop2-hdmi0-disp-modes-b39e3619768f