From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 42F1CCCD1BB for ; Wed, 22 Oct 2025 11:36:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:List-Subscribe:List-Help: List-Post:List-Archive:List-Unsubscribe:List-Id:Message-Id:Date:Subject:Cc:To :From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=tELWNrc567EuQ/hiTH45dYgNg0rNccON2VerNJIt6Ic=; b=gMfgWvHUwtoKnH V7OyFBaARiYAOXkGFhtoIxODs4kax/YQY2ID0ES7wub+BaXmsHsRbsO1MjU+Sey/TuqZKyVOyaV6d gl9wJkIoGgAtjsbSsmHJ16BECmoG1ieC95625IsDWXzO0SI0uKwoT+ZFuWDtRz2TJ68jtsPvLo9Ii 3wumAcx9TiWtbN3Hbb4O9eHoSSQOIJgX1zOI9Kdgt5gZZ5EI1Cjqi/jGvA1VcH2ELmEdQ5ibhJj/7 dld+ro4pJZKG+tvpsY2A150RMHOAdBGjjmTQLmC4megkdErKrB9jzay6kWLNejmzQpjOA06DFtUV7 KNs+T7OKQ74RHJNvwGiQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1vBX8Y-00000002fvx-4AI4; Wed, 22 Oct 2025 11:36:14 +0000 Received: from mail-m3297.qiye.163.com ([220.197.32.97]) by bombadil.infradead.org with esmtps (Exim 4.98.2 #2 (Red Hat Linux)) id 1vBX8N-00000002fp8-3fM6 for linux-rockchip@lists.infradead.org; Wed, 22 Oct 2025 11:36:11 +0000 Received: from localhost.localdomain (unknown [58.22.7.114]) by smtp.qiye.163.com (Hmail) with ESMTP id 26cdf437c; Wed, 22 Oct 2025 19:35:59 +0800 (GMT+08:00) From: Shawn Lin To: Heiko Stuebner , Manivannan Sadhasivam , Bjorn Helgaas Cc: linux-rockchip@lists.infradead.org, Niklas Cassel , linux-pci@vger.kernel.org, Shawn Lin Subject: [PATCH v2 1/2] PCI: dw-rockchip: Add L1sub support Date: Wed, 22 Oct 2025 19:35:53 +0800 Message-Id: <1761132954-177344-1-git-send-email-shawn.lin@rock-chips.com> X-Mailer: git-send-email 2.7.4 X-HM-Tid: 0a9a0bb454d609cckunm6eedc7d27fce0f X-HM-MType: 1 X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFDSUNOT01LS0k3V1ktWUFJV1kPCRoVCBIfWUFZGh8eQlZMQkxKHUJCHkkeTkNWFRQJFh oXVRMBExYaEhckFA4PWVdZGBILWUFZTkNVSUlVTFVKSk9ZV1kWGg8SFR0UWUFZT0tIVUpLSU9PT0 hVSktLVUpCS0tZBg++ DKIM-Signature: a=rsa-sha256; b=XZVpaBvnMFnzpqCTy5MAwII3sz1NvowwQynwbPyxebo/hmLxVBfLu5A2MJY7r3Fa7jTffRGQqiseMDR6gsoUIs3zv0QyyvJQOofYFIpbyiJ3AYR3QGB636/wTwwFekV63jyIIJU2TJgCD/GdVap7Is2QfREB38k7bBw6JAOc6nM=; s=default; c=relaxed/relaxed; d=rock-chips.com; v=1; bh=qOLHM+TrrAXVjum0eLPImVRVPBFYjL22w5LKZkowYSg=; h=date:mime-version:subject:message-id:from; X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20251022_043607_822643_26EEFDFC X-CRM114-Status: GOOD ( 14.74 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org The driver should set app_clk_req_n(clkreq ready) of PCIE_CLIENT_POWER reg to support L1sub. Otherwise, unset app_clk_req_n and pull down CLKREQ#. Signed-off-by: Shawn Lin --- Changes in v2: - drop of_pci_clkreq_presnt API - drop dependency of Niklas's patch drivers/pci/controller/dwc/pcie-dw-rockchip.c | 36 +++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c index 3e2752c..18cd626 100644 --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c @@ -62,6 +62,12 @@ /* Interrupt Mask Register Related to Miscellaneous Operation */ #define PCIE_CLIENT_INTR_MASK_MISC 0x24 +/* Power Management Control Register */ +#define PCIE_CLIENT_POWER 0x2c +#define PCIE_CLKREQ_READY 0x10001 +#define PCIE_CLKREQ_NOT_READY 0x10000 +#define PCIE_CLKREQ_PULL_DOWN 0x30001000 + /* Hot Reset Control Register */ #define PCIE_CLIENT_HOT_RESET_CTRL 0x180 #define PCIE_LTSSM_APP_DLY2_EN BIT(1) @@ -85,6 +91,7 @@ struct rockchip_pcie { struct regulator *vpcie3v3; struct irq_domain *irq_domain; const struct rockchip_pcie_of_data *data; + bool supports_clkreq; }; struct rockchip_pcie_of_data { @@ -200,6 +207,31 @@ static bool rockchip_pcie_link_up(struct dw_pcie *pci) return FIELD_GET(PCIE_LINKUP_MASK, val) == PCIE_LINKUP; } +static void rockchip_pcie_enable_l1sub(struct dw_pcie *pci) +{ + struct rockchip_pcie *rockchip = to_rockchip_pcie(pci); + u32 cap, l1subcap; + + /* Enable L1 substates if CLKREQ# is properly connected */ + if (rockchip->supports_clkreq) { + /* Ready to have reference clock removed */ + rockchip_pcie_writel_apb(rockchip, PCIE_CLKREQ_READY, PCIE_CLIENT_POWER); + return; + } + + /* Otherwise, pull down CLKREQ# and disable L1 substates */ + rockchip_pcie_writel_apb(rockchip, PCIE_CLKREQ_PULL_DOWN | PCIE_CLKREQ_NOT_READY, + PCIE_CLIENT_POWER); + cap = dw_pcie_find_ext_capability(pci, PCI_EXT_CAP_ID_L1SS); + if (cap) { + l1subcap = dw_pcie_readl_dbi(pci, cap + PCI_L1SS_CAP); + l1subcap &= ~(PCI_L1SS_CAP_L1_PM_SS | PCI_L1SS_CAP_ASPM_L1_1 | + PCI_L1SS_CAP_ASPM_L1_2 | PCI_L1SS_CAP_PCIPM_L1_1 | + PCI_L1SS_CAP_PCIPM_L1_2); + dw_pcie_writel_dbi(pci, cap + PCI_L1SS_CAP, l1subcap); + } +} + static void rockchip_pcie_enable_l0s(struct dw_pcie *pci) { u32 cap, lnkcap; @@ -264,6 +296,7 @@ static int rockchip_pcie_host_init(struct dw_pcie_rp *pp) irq_set_chained_handler_and_data(irq, rockchip_pcie_intx_handler, rockchip); + rockchip_pcie_enable_l1sub(pci); rockchip_pcie_enable_l0s(pci); return 0; @@ -301,6 +334,7 @@ static void rockchip_pcie_ep_init(struct dw_pcie_ep *ep) struct dw_pcie *pci = to_dw_pcie_from_ep(ep); enum pci_barno bar; + rockchip_pcie_enable_l1sub(pci); rockchip_pcie_enable_l0s(pci); rockchip_pcie_ep_hide_broken_ats_cap_rk3588(ep); @@ -412,6 +446,8 @@ static int rockchip_pcie_resource_get(struct platform_device *pdev, return dev_err_probe(&pdev->dev, PTR_ERR(rockchip->rst), "failed to get reset lines\n"); + rockchip->supports_clkreq = of_property_read_bool(pdev->dev.of_node, "supports-clkreq"); + return 0; } -- 2.7.4 _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip