From mboxrd@z Thu Jan 1 00:00:00 1970 From: Heiko =?ISO-8859-1?Q?St=FCbner?= Subject: Re: [RESEND PATCH] clk: rockchip: Prevent calculating mmc phase if clock rate is zero Date: Mon, 05 Mar 2018 22:08:52 +0100 Message-ID: <1992472.PuCZ8TM9rV@diego> References: <1520220358-181119-1-git-send-email-shawn.lin@rock-chips.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: In-Reply-To: <1520220358-181119-1-git-send-email-shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+glpar-linux-rockchip=m.gmane.org-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org To: Shawn Lin Cc: Stephen Boyd , linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, Michael Turquette , linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org List-Id: linux-rockchip.vger.kernel.org Am Montag, 5. M=E4rz 2018, 04:25:58 CET schrieb Shawn Lin: > The MMC sample and drv clock for rockchip platforms are derived from > the bus clock output to the MMC/SDIO card. So it should never happens > that the clk rate is zero given it should inherits the clock rate from > its parent. If something goes wrong and makes the clock rate to be zero, > the calculation would be wrong but may still make the mmc tuning process > work luckily. However it makes people harder to debug when the following > data transfer is unstable. > = > Signed-off-by: Shawn Lin applied for 4.17 Thanks Heiko