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From: Brian Norris <briannorris@chromium.org>
To: Shawn Lin <shawn.lin@rock-chips.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>,
	Kishon Vijay Abraham I <kishon@ti.com>,
	Rob Herring <robh@kernel.org>, Heiko Stuebner <heiko@sntech.de>,
	linux-pci@vger.kernel.org, linux-rockchip@lists.infradead.org,
	Jeffy Chen <jeffy.chen@rock-chips.com>,
	devicetree@vger.kernel.org
Subject: Re: [RFC PATCH v3 2/7] PCI: rockchip: introduce per-lanes PHYs support
Date: Tue, 18 Jul 2017 13:33:36 -0700	[thread overview]
Message-ID: <20170718203335.GC116895@google.com> (raw)
In-Reply-To: <1500364623-97041-3-git-send-email-shawn.lin@rock-chips.com>

Hi,

On Tue, Jul 18, 2017 at 03:56:58PM +0800, Shawn Lin wrote:
> We distinguish the legacy PHY with the newer per-lane
> PHYs by adding legacy_phy flag. Note that the legacy phy
> is still the first option to be searched in order not to
> break the backward compatibility of DTB.
> 
> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
> Tested-by: Jeffy Chen <jeffy.chen@rock-chips.com>
> ---
> 
> Changes in v3:
> - kill rockchip_pcie_manipulate_phys and related stuff
> - use phys array
> - improve the commit msg
> 
> Changes in v2: None
> 
>  drivers/pci/host/pcie-rockchip.c | 100 +++++++++++++++++++++++++++------------
>  1 file changed, 69 insertions(+), 31 deletions(-)
> 
> diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c
> index 6632a51..4cc6aec 100644
> --- a/drivers/pci/host/pcie-rockchip.c
> +++ b/drivers/pci/host/pcie-rockchip.c

...

> @@ -537,10 +579,12 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
>  		return err;
>  	}
>  
> -	err = phy_init(rockchip->phy);
> -	if (err < 0) {
> -		dev_err(dev, "fail to init phy, err %d\n", err);
> -		return err;
> +	for (i = 0; i < MAX_LANE_NUM; i++) {
> +		err = phy_init(rockchip->phys[i]);
> +		if (err) {
> +			dev_err(dev, "init phy err %d\n", err);

Include the PHY index in the error message?

> +			return err;
> +		}
>  	}
>  
>  	err = reset_control_assert(rockchip->core_rst);
> @@ -602,10 +646,12 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
>  			    PCIE_CLIENT_MODE_RC,
>  			    PCIE_CLIENT_CONFIG);
>  
> -	err = phy_power_on(rockchip->phy);
> -	if (err) {
> -		dev_err(dev, "fail to power on phy, err %d\n", err);
> -		return err;
> +	for (i = 0; i < MAX_LANE_NUM; i++) {
> +		err = phy_power_on(rockchip->phys[i]);
> +		if (err) {
> +			dev_err(dev, "power on phy err %d\n", err);

Same?

> +			return err;
> +		}
>  	}
>  
>  	/*

...

Brian

  reply	other threads:[~2017-07-18 20:33 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-07-18  7:56 [RFC PATCH v3 0/7] Reconstruct rockchip's PCIe and PCIe-PHY driver for per-lane PHY model Shawn Lin
     [not found] ` <1500364623-97041-1-git-send-email-shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
2017-07-18  7:56   ` [RFC PATCH v3 1/7] PCI: rockchip: split out rockchip_pcie_get_phys Shawn Lin
     [not found]     ` <1500364623-97041-2-git-send-email-shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
2017-07-18 20:31       ` Brian Norris
2017-07-18  7:56   ` [RFC PATCH v3 2/7] PCI: rockchip: introduce per-lanes PHYs support Shawn Lin
2017-07-18 20:33     ` Brian Norris [this message]
2017-07-18  7:56   ` [RFC PATCH v3 3/7] phy: rockcip-pcie: reconstruct driver to support per-lane PHYs Shawn Lin
2017-07-18 20:29   ` [RFC PATCH v3 0/7] Reconstruct rockchip's PCIe and PCIe-PHY driver for per-lane PHY model Brian Norris
2017-07-19  0:51     ` Shawn Lin
2017-07-18  7:57 ` [RFC PATCH v3 4/7] PCI: rockchip: idle the inactive PHY(s) Shawn Lin
     [not found]   ` <1500364623-97041-5-git-send-email-shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
2017-07-18 20:39     ` Brian Norris
2017-07-18  7:59 ` [RFC PATCH v3 5/7] arm64: dts: rockchip: convert PCIe to use per-lane PHYs for rk3339 Shawn Lin
2017-07-18  7:59   ` [RFC PATCH v3 6/7] dt-bindings: PCI: rockchip: convert to use per-lane PHY model Shawn Lin
2017-07-18  7:59   ` [RFC PATCH v3 7/7] dt-bindings: phy: convert to use per-lane Rockchip PCIe PHY Shawn Lin

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