[PATCH 33/92] ram: rk3399: Order tsel variables

Jagan Teki
2019-06-11T14:50:36Z

Order tsel* variable declarations and assignment in proper
and meaningful way.

No functionality change.

Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Signed-off-by: YouMin Chen <cym-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---
drivers/ram/rockchip/sdram_rk3399.c | 37 +++++++++++++++++------------
1 file changed, 22 insertions(+), 15 deletions(-)

diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index d868621c93..e3945feca3 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -160,41 +160,48 @@ static void set_ds_odt(const struct chan_info *chan,
u32 *denali_phy = chan->publ->denali_phy;

u32 tsel_idle_en, tsel_wr_en, tsel_rd_en;
- u32 tsel_idle_select_p, tsel_wr_select_dq_p, tsel_rd_select_p;
- u32 tsel_wr_select_ca_p, tsel_wr_select_ca_n;
- u32 tsel_idle_select_n, tsel_wr_select_dq_n, tsel_rd_select_n;
+ u32 tsel_idle_select_p, tsel_rd_select_p;
+ u32 tsel_idle_select_n, tsel_rd_select_n;
+ u32 tsel_wr_select_dq_p, tsel_wr_select_ca_p;
+ u32 tsel_wr_select_dq_n, tsel_wr_select_ca_n;
u32 reg_value;

if (sdram_params->base.dramtype == LPDDR4) {
tsel_rd_select_p = PHY_DRV_ODT_HI_Z;
- tsel_wr_select_dq_p = PHY_DRV_ODT_40;
- tsel_wr_select_ca_p = PHY_DRV_ODT_40;
+ tsel_rd_select_n = PHY_DRV_ODT_240;
+
tsel_idle_select_p = PHY_DRV_ODT_HI_Z;
+ tsel_idle_select_n = PHY_DRV_ODT_240;

- tsel_rd_select_n = PHY_DRV_ODT_240;
+ tsel_wr_select_dq_p = PHY_DRV_ODT_40;
tsel_wr_select_dq_n = PHY_DRV_ODT_40;
+
+ tsel_wr_select_ca_p = PHY_DRV_ODT_40;
tsel_wr_select_ca_n = PHY_DRV_ODT_40;
- tsel_idle_select_n = PHY_DRV_ODT_240;
} else if (sdram_params->base.dramtype == LPDDR3) {
tsel_rd_select_p = PHY_DRV_ODT_240;
- tsel_wr_select_dq_p = PHY_DRV_ODT_34_3;
- tsel_wr_select_ca_p = PHY_DRV_ODT_48;
+ tsel_rd_select_n = PHY_DRV_ODT_HI_Z;
+
tsel_idle_select_p = PHY_DRV_ODT_240;
+ tsel_idle_select_n = PHY_DRV_ODT_HI_Z;

- tsel_rd_select_n = PHY_DRV_ODT_HI_Z;
+ tsel_wr_select_dq_p = PHY_DRV_ODT_34_3;
tsel_wr_select_dq_n = PHY_DRV_ODT_34_3;
+
+ tsel_wr_select_ca_p = PHY_DRV_ODT_48;
tsel_wr_select_ca_n = PHY_DRV_ODT_48;
- tsel_idle_select_n = PHY_DRV_ODT_HI_Z;
} else {
tsel_rd_select_p = PHY_DRV_ODT_240;
- tsel_wr_select_dq_p = PHY_DRV_ODT_34_3;
- tsel_wr_select_ca_p = PHY_DRV_ODT_34_3;
+ tsel_rd_select_n = PHY_DRV_ODT_240;
+
tsel_idle_select_p = PHY_DRV_ODT_240;
+ tsel_idle_select_n = PHY_DRV_ODT_240;

- tsel_rd_select_n = PHY_DRV_ODT_240;
+ tsel_wr_select_dq_p = PHY_DRV_ODT_34_3;
tsel_wr_select_dq_n = PHY_DRV_ODT_34_3;
+
+ tsel_wr_select_ca_p = PHY_DRV_ODT_34_3;
tsel_wr_select_ca_n = PHY_DRV_ODT_34_3;
- tsel_idle_select_n = PHY_DRV_ODT_240;
}

if (sdram_params->base.odt == 1)
--
2.18.0.321.gffc6fa0e3