Re: [PATCH] arm64: dts: rockchip: Describe PX30 caches

[Miquel Raynal <miquel.raynal-LDxbnhwyfcJBDgjK7y7TUQ@public.gmane.org>]

Hi Peter,

Peter Geis <pgwipeout@gmail.com> wrote on Wed, 4 Dec 2019 10:36:19
-0500:

> On Wed, Dec 4, 2019 at 5:40 AM Miquel Raynal <miquel.raynal@bootlin.com> wrote:
> >
> > PX30 SoCs feature 4 Cortex-A35 CPUs with each of them a L1 data and
> > instruction cache. Both are 32kiB wide (PX30 TRM) and made of 64-bit
> > lines (ARM Cortex-A35 manual). I-cache is 2-way set associative (ARM
> > Cortex-A35 manual), D-cache is 4-way set associative (ARM
> > Cortex-A35manual).
> >
> > An L2 cache is placed after these 4 L1 caches (PX30 TRM), is 256kiB
> > wide (PX30 TRM) and made of 64-bit lines (ARM Cortex-A35 manual) and
> > is 8-way set associative (ARM Cortex-A35 manual).
> >
> > Describe all of them in the PX30 DTSI.
> >
> > Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
> > ---
> >  arch/arm64/boot/dts/rockchip/px30.dtsi | 35 ++++++++++++++++++++++++++
> >  1 file changed, 35 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi b/arch/arm64/boot/dts/rockchip/px30.dtsi
> > index 1fd12bd09e83..0e10a224a84b 100644
> > --- a/arch/arm64/boot/dts/rockchip/px30.dtsi
> > +++ b/arch/arm64/boot/dts/rockchip/px30.dtsi
> > @@ -48,6 +48,13 @@
> >                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
> >                         dynamic-power-coefficient = <90>;
> >                         operating-points-v2 = <&cpu0_opp_table>;
> > +                       i-cache-size = <0x8000>;
> > +                       i-cache-line-size = <64>;
> > +                       i-cache-sets = <256>;
> > +                       d-cache-size = <0x8000>;
> > +                       d-cache-line-size = <64>;
> > +                       d-cache-sets = <128>;
> > +                       next-level-cache = <&l2>;  
> 
> If the i-cache is 2-way associative and the d-cache is 4-way, wouldn't
> that mean these two values are backwards?

Which value are you referring to? Do you mean cache-sets? The following
calculation is my understanding of the situation but it is the first
time I am doing it so I might be totally wrong.

My understanding is that if there are 32768 cache bytes made of 64-byte
lines, so there are 512 lines in both cases.

Then, if the instruction cache is 2-way associative, it means there are
512 / 2 = 256 sets. For the data cache (4-way), it would be 512 / 4 =
128. Am I wrong?

Thanks,
Miquèl

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