From mboxrd@z Thu Jan 1 00:00:00 1970 From: Rob Herring Subject: [PATCH 07/19] PCI: xilinx-nwl: Use pci_is_root_bus() to check if bus is root bus Date: Tue, 21 Jul 2020 20:25:02 -0600 Message-ID: <20200722022514.1283916-8-robh@kernel.org> References: <20200722022514.1283916-1-robh@kernel.org> Mime-Version: 1.0 Content-Transfer-Encoding: 8bit Return-path: In-Reply-To: <20200722022514.1283916-1-robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> Sender: linux-tegra-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Bjorn Helgaas , Lorenzo Pieralisi Cc: Fabio Estevam , Gustavo Pimentel , Heiko Stuebner , Hou Zhiqiang , Jingoo Han , Jonathan Hunter , Karthikeyan Mitran , Linus Walleij , Lucas Stach , Marek Vasut , Michal Simek , Murali Karicheri , NXP Linux Team , Pengutronix Kernel Team , Richard Zhu , Ryder Lee , Sascha Hauer , Shawn Guo , Shawn Lin List-Id: linux-rockchip.vger.kernel.org Use pci_is_root_bus() rather than tracking the root bus number to determine if the bus is the root bus or not. This removes storing duplicated data as well as the need for the host bridge driver to have to care about the bus numbers in most cases. There was also a bug that the pci_host_bridge.busnr is set from root_busno, but root_busno is never set which means the root bus number is always 0 even if the DT said something else. Cc: Lorenzo Pieralisi Cc: Bjorn Helgaas Cc: Michal Simek Signed-off-by: Rob Herring --- drivers/pci/controller/pcie-xilinx-nwl.c | 10 +++------- 1 file changed, 3 insertions(+), 7 deletions(-) diff --git a/drivers/pci/controller/pcie-xilinx-nwl.c b/drivers/pci/controller/pcie-xilinx-nwl.c index 3c747aa4b6d1..566165c18fad 100644 --- a/drivers/pci/controller/pcie-xilinx-nwl.c +++ b/drivers/pci/controller/pcie-xilinx-nwl.c @@ -166,7 +166,6 @@ struct nwl_pcie { int irq_misc; u32 ecam_value; u8 last_busno; - u8 root_busno; struct nwl_msi msi; struct irq_domain *legacy_irq_domain; raw_spinlock_t leg_mask_lock; @@ -217,13 +216,11 @@ static bool nwl_pcie_valid_device(struct pci_bus *bus, unsigned int devfn) struct nwl_pcie *pcie = bus->sysdata; /* Check link before accessing downstream ports */ - if (bus->number != pcie->root_busno) { + if (!pci_is_root_bus(bus)) { if (!nwl_pcie_link_up(pcie)) return false; - } - - /* Only one device down on each root port */ - if (bus->number == pcie->root_busno && devfn > 0) + } else if (devfn > 0) + /* Only one device down on each root port */ return false; return true; @@ -855,7 +852,6 @@ static int nwl_pcie_probe(struct platform_device *pdev) } bridge->sysdata = pcie; - bridge->busnr = pcie->root_busno; bridge->ops = &nwl_pcie_ops; bridge->map_irq = of_irq_parse_and_map_pci; bridge->swizzle_irq = pci_common_swizzle; -- 2.25.1