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[76.183.134.35]) by smtp.gmail.com with ESMTPSA id r7sm1219084oom.46.2021.05.28.10.00.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 May 2021 10:00:31 -0700 (PDT) From: Chris Morgan To: linux-mtd@lists.infradead.org Cc: linux-rockchip@lists.infradead.org, andy.yan@rock-chips.com, yifeng.zhao@rock-chips.com, sugar.zhang@rock-chips.com, tudor.ambarus@microchip.com, michael@walle.cc, p.yadav@ti.com, heiko@sntech.de, robh+dt@kernel.org, vigneshr@ti.com, richard@nod.at, miquel.raynal@bootlin.com, Chris Morgan Subject: [PATCH v2 3/4] arm64: dts: rockchip: Add SFC to PX30 Date: Fri, 28 May 2021 12:00:19 -0500 Message-Id: <20210528170020.26219-4-macroalpha82@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210528170020.26219-1-macroalpha82@gmail.com> References: <20210528170020.26219-1-macroalpha82@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210528_100033_676761_9F44E73E X-CRM114-Status: UNSURE ( 9.96 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org From: Chris Morgan Add a devicetree entry for the Rockchip SFC for the PX30 SOC. Signed-off-by: Chris Morgan --- arch/arm64/boot/dts/rockchip/px30.dtsi | 38 ++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi b/arch/arm64/boot/dts/rockchip/px30.dtsi index 09baa8a167ce..36fdfa06e83e 100644 --- a/arch/arm64/boot/dts/rockchip/px30.dtsi +++ b/arch/arm64/boot/dts/rockchip/px30.dtsi @@ -966,6 +966,18 @@ emmc: mmc@ff390000 { status = "disabled"; }; + sfc: spi@ff3a0000 { + compatible = "rockchip,px30-sfc","rockchip,sfc"; + reg = <0x0 0xff3a0000 0x0 0x4000>; + interrupts = ; + clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; + clock-names = "clk-sfc", "clk-hsfc"; + pinctrl-names = "default"; + pinctrl-0 = <&sfc_clk &sfc_cs &sfc_bus4>; + power-domains = <&power PX30_PD_MMC_NAND>; + status = "disabled"; + }; + nfc: nand-controller@ff3b0000 { compatible = "rockchip,px30-nfc"; reg = <0x0 0xff3b0000 0x0 0x4000>; @@ -1967,6 +1979,32 @@ flash_bus8: flash-bus8 { }; }; + serial_flash { + sfc_bus4: sfc-bus4 { + rockchip,pins = + <1 RK_PA0 3 &pcfg_pull_none>, + <1 RK_PA1 3 &pcfg_pull_none>, + <1 RK_PA2 3 &pcfg_pull_none>, + <1 RK_PA3 3 &pcfg_pull_none>; + }; + + sfc_bus2: sfc-bus2 { + rockchip,pins = + <1 RK_PA0 3 &pcfg_pull_none>, + <1 RK_PA1 3 &pcfg_pull_none>; + }; + + sfc_cs: sfc-cs { + rockchip,pins = + <1 RK_PA4 3 &pcfg_pull_none>; + }; + + sfc_clk: sfc-clk { + rockchip,pins = + <1 RK_PB1 3 &pcfg_pull_none>; + }; + }; + lcdc { lcdc_rgb_dclk_pin: lcdc-rgb-dclk-pin { rockchip,pins = -- 2.25.1 _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip