Re: [PATCH v1] arm64: dts: rockchip: Add sata2 node to rk356x

Peter Geis
2022-02-26T18:16:20Z

On Sat, Feb 26, 2022 at 1:08 PM Heiko Stübner <heiko@sntech.de> wrote:
>
> Hi Frank,
>
> Am Samstag, 26. Februar 2022, 14:57:24 CET schrieb Frank Wunderlich:
> > From: Frank Wunderlich <frank-w@public-files.de>
> >
> > RK356x supports up to 3 sata controllers which were compatible with the
> > existing snps,dwc-ahci binding.
> >
> > My board has only sata2 connected to combphy2 so only add this one.
>
> how far does the added node diverge from the vendor kernel?
>
> If it's pretty much similar between both, we can assume the other nodes
> should work pretty well as well and therefore should all of them at once
> and hope for the best?

There's essentially zero divergence (minus the change due to combophy
changing), and likely won't be until the ahci-platform.txt is
converted to yaml.

I have tested both SATA1 and SATA2 successfully on the rk3566.
I don't have any rk3568 boards that are operational yet to test SATA0.

>
> Thanks
> Heiko
>
> > Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
> > ---
> > arch/arm64/boot/dts/rockchip/rk356x.dtsi | 15 +++++++++++++++
> > 1 file changed, 15 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
> > index 7cdef800cb3c..7b6c8a0c8b84 100644
> > --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
> > +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
> > @@ -230,6 +230,21 @@ scmi_shmem: sram@0 {
> > };
> > };
> >
> > + sata2: sata@fc800000 {
> > + compatible = "snps,dwc-ahci";
> > + reg = <0 0xfc800000 0 0x1000>;
> > + clocks = <&cru ACLK_SATA2>, <&cru CLK_SATA2_PMALIVE>,
> > + <&cru CLK_SATA2_RXOOB>;
> > + clock-names = "sata", "pmalive", "rxoob";
> > + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
> > + interrupt-names = "hostc";
> > + phys = <&combphy2 PHY_TYPE_SATA>;
> > + phy-names = "sata-phy";
> > + ports-implemented = <0x1>;
> > + power-domains = <&power RK3568_PD_PIPE>;
> > + status = "disabled";
> > + };
> > +
> > gic: interrupt-controller@fd400000 {
> > compatible = "arm,gic-v3";
> > reg = <0x0 0xfd400000 0 0x10000>, /* GICD */
> >