From: Peter Geis <pgwipeout@gmail.com>
To: Felipe Balbi <balbi@kernel.org>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: linux-rockchip@lists.infradead.org, heiko@sntech.de,
michael.riesch@wolfvision.net, Bin Yang <yangbin@rock-chips.com>,
Peter Geis <pgwipeout@gmail.com>,
linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: [PATCH v2 05/11] usb: dwc3: core: do not use 3.0 clock when operating in 2.0 mode
Date: Sat, 26 Feb 2022 13:41:41 -0500 [thread overview]
Message-ID: <20220226184147.769964-6-pgwipeout@gmail.com> (raw)
In-Reply-To: <20220226184147.769964-1-pgwipeout@gmail.com>
From: Bin Yang <yangbin@rock-chips.com>
In the 3.0 device core, if the core is programmed to operate in
2.0 only, then setting the GUCTL1.DEV_FORCE_20_CLK_FOR_30_CLK makes
the internal 2.0(utmi/ulpi) clock to be routed as the 3.0 (pipe)
clock. Enabling this feature allows the pipe3 clock to be not-running
when forcibly operating in 2.0 device mode.
Signed-off-by: Bin Yang <yangbin@rock-chips.com>
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
---
drivers/usb/dwc3/core.c | 5 +++++
drivers/usb/dwc3/core.h | 1 +
2 files changed, 6 insertions(+)
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index 18adddfba3da..416d83a055fe 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -1167,6 +1167,11 @@ static int dwc3_core_init(struct dwc3 *dwc)
if (dwc->parkmode_disable_ss_quirk)
reg |= DWC3_GUCTL1_PARKMODE_DISABLE_SS;
+ if (DWC3_VER_IS_WITHIN(DWC3, 290A, ANY) &&
+ (dwc->maximum_speed == USB_SPEED_HIGH ||
+ dwc->maximum_speed == USB_SPEED_FULL))
+ reg |= DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK;
+
dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
}
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index eb9c1efced05..ea3ca04406bb 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -259,6 +259,7 @@
/* Global User Control 1 Register */
#define DWC3_GUCTL1_DEV_DECOUPLE_L1L2_EVT BIT(31)
#define DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS BIT(28)
+#define DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK BIT(26)
#define DWC3_GUCTL1_DEV_L1_EXIT_BY_HW BIT(24)
#define DWC3_GUCTL1_PARKMODE_DISABLE_SS BIT(17)
--
2.25.1
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next prev parent reply other threads:[~2022-02-26 18:43 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-26 18:41 [PATCH v2 00/11] enable usb support on rk356x Peter Geis
2022-02-26 18:41 ` [PATCH v2 01/11] dt-bindings: soc: grf: fix rk3568 usb definitions Peter Geis
2022-02-26 18:41 ` [PATCH v2 02/11] dt-bindings: soc: grf: add rk3566-pipe-grf compatible Peter Geis
2022-02-26 18:41 ` [PATCH v2 03/11] dt-bindings: usb: dwc3: add description for rk3568 Peter Geis
2022-03-04 23:13 ` Rob Herring
2022-02-26 18:41 ` [PATCH v2 04/11] soc: rockchip: set dwc3 clock for rk3566 Peter Geis
2022-02-26 18:41 ` Peter Geis [this message]
2022-02-26 18:41 ` [PATCH v2 06/11] usb: dwc3: reorder dwc-of-simple compatibles Peter Geis
2022-02-26 18:41 ` [PATCH v2 07/11] usb: dwc3: convert dwc3-of-simple to use match-data Peter Geis
2022-02-26 18:41 ` [PATCH v2 08/11] usb: dwc3: add rk3568 dwc3 support Peter Geis
2022-02-26 21:43 ` Johan Jonker
2022-02-26 23:48 ` Peter Geis
2022-02-26 18:41 ` [PATCH v2 09/11] arm64: dts: rockchip: add rk356x dwc3 usb3 nodes Peter Geis
2022-02-26 23:01 ` Johan Jonker
2022-02-27 13:56 ` Peter Geis
2022-02-26 18:41 ` [PATCH v2 10/11] arm64: dts: rockchip: enable dwc3 on quartz64-a Peter Geis
2022-02-26 18:41 ` [PATCH v2 11/11] arm64: dts: rockchip: add usb3 support to rk3568-evb1-v10 Peter Geis
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