From: Jianqun Xu <jay.xu@rock-chips.com>
To: linus.walleij@linaro.org, heiko@sntech.de
Cc: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org,
linux-gpio@vger.kernel.org, linux-rockchip@lists.infradead.org,
Jianqun Xu <jay.xu@rock-chips.com>
Subject: [PATCH 2/2] arm64: dts: rockchip: rk356x add 'clock-names' for gpio nodes
Date: Thu, 1 Sep 2022 09:29:42 +0800 [thread overview]
Message-ID: <20220901012944.2634398-4-jay.xu@rock-chips.com> (raw)
In-Reply-To: <20220901012944.2634398-1-jay.xu@rock-chips.com>
Add 'clock-names' for gpio nodes on rk356x SoCs, after this patch, the
gpio driver can get the clocks by a const char id, 'bus' for apb clock
and 'db' for the debounce clock.
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
---
arch/arm64/boot/dts/rockchip/rk356x.dtsi | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
index 319981c3e9f7..66d038720e65 100644
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
@@ -1650,6 +1650,7 @@ gpio0: gpio@fdd60000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0xfdd60000 0x0 0x100>;
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "bus", "db";
clocks = <&pmucru PCLK_GPIO0>, <&pmucru DBCLK_GPIO0>;
gpio-controller;
#gpio-cells = <2>;
@@ -1661,6 +1662,7 @@ gpio1: gpio@fe740000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0xfe740000 0x0 0x100>;
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "bus", "db";
clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
gpio-controller;
#gpio-cells = <2>;
@@ -1672,6 +1674,7 @@ gpio2: gpio@fe750000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0xfe750000 0x0 0x100>;
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "bus", "db";
clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
gpio-controller;
#gpio-cells = <2>;
@@ -1683,6 +1686,7 @@ gpio3: gpio@fe760000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0xfe760000 0x0 0x100>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "bus", "db";
clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
gpio-controller;
#gpio-cells = <2>;
@@ -1694,6 +1698,7 @@ gpio4: gpio@fe770000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0xfe770000 0x0 0x100>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "bus", "db";
clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;
gpio-controller;
#gpio-cells = <2>;
--
2.25.1
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next prev parent reply other threads:[~2022-09-01 1:30 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-01 1:29 [PATCH 0/2] gpio clock-names Jianqun Xu
2022-09-01 1:29 ` [PATCH 1/2] dt-bindings: gpio: rockchip: add clock-names Jianqun Xu
2022-09-01 11:48 ` Rob Herring
2022-09-02 0:48 ` jay.xu
2022-09-01 1:29 ` [PATCH v1 1/3] gpio: rockchip: make gpio work without cru module Jianqun Xu
2022-09-02 18:38 ` Peter Geis
2022-09-02 21:09 ` Heiko Stübner
2022-09-01 1:29 ` Jianqun Xu [this message]
2022-09-01 1:29 ` [PATCH 2/3] gpio: rockchip: get pinctrl node from 'gpio-ranges' property Jianqun Xu
2022-09-01 1:29 ` [PATCH 3/3] dt-bindings: gpio: rockchip,gpio add optional 'gpio-ranges' Jianqun Xu
2022-09-01 13:32 ` Krzysztof Kozlowski
-- strict thread matches above, loose matches on Subject: below --
2022-09-01 1:30 [PATCH 0/2] gpio clock-names Jianqun Xu
2022-09-01 1:31 ` [PATCH 2/2] arm64: dts: rockchip: rk356x add 'clock-names' for gpio nodes Jianqun Xu
2022-09-02 6:04 [PATCH 0/2] gpio clock-names Jianqun Xu
2022-09-02 6:04 ` [PATCH 2/2] arm64: dts: rockchip: rk356x add 'clock-names' for gpio nodes Jianqun Xu
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