Re: [PATCH v4 05/13] clk: rockchip: Add clock controller support for RV1126 SoC.

Heiko Stuebner
2022-09-13T10:13:36Z

Hi Jagan,

Am Mittwoch, 7. September 2022, 18:01:59 CEST schrieb Jagan Teki:
> Clock & Reset Unit (CRU) in RV1126 support clocks for CRU
> and CRU_PMU blocks.
>
> This patch is trying to add minimal Clock-Architecture Diagram's
> inferred from [1] authored by Finley Xiao.
>
> [1] https://github.com/rockchip-linux/kernel/blob/develop-4.19/drivers/clk/rockchip/clk-rv1126.c
>
> Cc: linux-clk@vger.kernel.org
> Cc: Michael Turquette <mturquette@baylibre.com>
> Cc: Stephen Boyd <sboyd@kernel.org>
> Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
> Signed-off-by: Jagan Teki <jagan@edgeble.ai>
> ---

[...]

> +static void __init rv1126_pmu_clk_init(struct device_node *np)
> +{
> + struct rockchip_clk_provider *ctx;
> + void __iomem *reg_base;
> +
> + reg_base = of_iomap(np, 0);
> + if (!reg_base) {
> + pr_err("%s: could not map cru pmu region\n", __func__);
> + return;
> + }
> +
> + ctx = rockchip_clk_init(np, reg_base, CLKPMU_NR_CLKS);
> + if (IS_ERR(ctx)) {
> + pr_err("%s: rockchip pmu clk init failed\n", __func__);
> + return;
> + }
> +
> + rockchip_clk_register_plls(ctx, rv1126_pmu_pll_clks,
> + ARRAY_SIZE(rv1126_pmu_pll_clks),
> + RV1126_GRF_SOC_STATUS0);
> +
> + rockchip_clk_register_branches(ctx, rv1126_clk_pmu_branches,
> + ARRAY_SIZE(rv1126_clk_pmu_branches));
> +
> + rockchip_register_softrst(np, 2, reg_base + RV1126_PMU_SOFTRST_CON(0),
> + ROCKCHIP_SOFTRST_HIWORD_MASK);
> +
> + rockchip_clk_of_add_provider(np, ctx);
> +}
> +
> +CLK_OF_DECLARE(rv1126_cru_pmu, "rockchip,rv1126-pmucru", rv1126_pmu_clk_init);

both of these want to be platform-drivers nowadays.

Take a look at rk3399 and rk3568 for reference.

Thanks
Heiko

> +
> +static void __init rv1126_clk_init(struct device_node *np)
> +{
> + struct rockchip_clk_provider *ctx;
> + void __iomem *reg_base;
> +
> + reg_base = of_iomap(np, 0);
> + if (!reg_base) {
> + pr_err("%s: could not map cru region\n", __func__);
> + return;
> + }
> +
> + ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
> + if (IS_ERR(ctx)) {
> + pr_err("%s: rockchip clk init failed\n", __func__);
> + iounmap(reg_base);
> + return;
> + }
> +
> + rockchip_clk_register_plls(ctx, rv1126_pll_clks,
> + ARRAY_SIZE(rv1126_pll_clks),
> + RV1126_GRF_SOC_STATUS0);
> +
> + rockchip_clk_register_armclk(ctx, ARMCLK, "armclk",
> + mux_armclk_p, ARRAY_SIZE(mux_armclk_p),
> + &rv1126_cpuclk_data, rv1126_cpuclk_rates,
> + ARRAY_SIZE(rv1126_cpuclk_rates));
> +
> + rockchip_clk_register_branches(ctx, rv1126_clk_branches,
> + ARRAY_SIZE(rv1126_clk_branches));
> +
> + rockchip_register_softrst(np, 15, reg_base + RV1126_SOFTRST_CON(0),
> + ROCKCHIP_SOFTRST_HIWORD_MASK);
> +
> + rockchip_register_restart_notifier(ctx, RV1126_GLB_SRST_FST, NULL);
> +
> + rockchip_clk_protect_critical(rv1126_cru_critical_clocks,
> + ARRAY_SIZE(rv1126_cru_critical_clocks));
> +
> + rockchip_clk_of_add_provider(np, ctx);
> +}
> +
> +CLK_OF_DECLARE(rv1126_cru, "rockchip,rv1126-cru", rv1126_clk_init);