Hi Benjamin, I love your patch! Perhaps something to improve: [auto build test WARNING on media-tree/master] [also build test WARNING on rockchip/for-next linus/master v6.2-rc2 next-20221226] [cannot apply to pza/reset/next pza/imx-drm/next] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch#_base_tree_information] url: https://github.com/intel-lab-lkp/linux/commits/Benjamin-Gaignard/dt-bindings-media-rockchip-vpu-Add-rk3588-vpu-compatible/20230104-010906 base: git://linuxtv.org/media_tree.git master patch link: https://lore.kernel.org/r/20230103170058.810597-11-benjamin.gaignard%40collabora.com patch subject: [PATCH v2 10/13] media: verisilicon: Add Rockchip AV1 decoder config: sh-allmodconfig compiler: sh4-linux-gcc (GCC) 12.1.0 reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # https://github.com/intel-lab-lkp/linux/commit/9223ba771533395ef28d21c8b4c944dde145d820 git remote add linux-review https://github.com/intel-lab-lkp/linux git fetch --no-tags linux-review Benjamin-Gaignard/dt-bindings-media-rockchip-vpu-Add-rk3588-vpu-compatible/20230104-010906 git checkout 9223ba771533395ef28d21c8b4c944dde145d820 # save the config file mkdir build_dir && cp config build_dir/.config COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross W=1 O=build_dir ARCH=sh olddefconfig COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross W=1 O=build_dir ARCH=sh SHELL=/bin/bash drivers/media/platform/verisilicon/ If you fix the issue, kindly add following tag where applicable | Reported-by: kernel test robot All warnings (new ones prefixed by >>): drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c:229:6: warning: no previous prototype for 'rockchip_vpu981_av1_dec_tiles_free' [-Wmissing-prototypes] 229 | void rockchip_vpu981_av1_dec_tiles_free(struct hantro_ctx *ctx) | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c:327:6: warning: no previous prototype for 'rockchip_vpu981_av1_dec_exit' [-Wmissing-prototypes] 327 | void rockchip_vpu981_av1_dec_exit(struct hantro_ctx *ctx) | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c:363:5: warning: no previous prototype for 'rockchip_vpu981_av1_dec_init' [-Wmissing-prototypes] 363 | int rockchip_vpu981_av1_dec_init(struct hantro_ctx *ctx) | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c: In function 'rockchip_vpu981_av1_dec_set_segmentation': drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c:790:47: warning: variable 'chroma_addr' set but not used [-Wunused-but-set-variable] 790 | dma_addr_t luma_addr, chroma_addr, mv_addr = 0; | ^~~~~~~~~~~ drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c: At top level: drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c:1141:6: warning: no previous prototype for 'rockchip_vpu981_av1_dec_done' [-Wmissing-prototypes] 1141 | void rockchip_vpu981_av1_dec_done(struct hantro_ctx *ctx) | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c:1933:5: warning: no previous prototype for 'rockchip_vpu981_av1_dec_run' [-Wmissing-prototypes] 1933 | int rockchip_vpu981_av1_dec_run(struct hantro_ctx *ctx) | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c: In function 'rockchip_vpu981_av1_dec_set_tile_info': >> drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c:616:1: warning: the frame size of 1076 bytes is larger than 1024 bytes [-Wframe-larger-than=] 616 | } | ^ vim +616 drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c 546 547 static void rockchip_vpu981_av1_dec_set_tile_info(struct hantro_ctx *ctx) 548 { 549 struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec; 550 struct hantro_av1_dec_ctrls *ctrls = &av1_dec->ctrls; 551 struct v4l2_av1_tile_info tile_info = ctrls->frame->tile_info; 552 const struct v4l2_ctrl_av1_tile_group_entry *group_entry = 553 ctrls->tile_group_entry; 554 int context_update_y = 555 tile_info.context_update_tile_id / tile_info.tile_cols; 556 int context_update_x = 557 tile_info.context_update_tile_id % tile_info.tile_cols; 558 int context_update_tile_id = 559 context_update_x * tile_info.tile_rows + context_update_y; 560 uint8_t *dst = av1_dec->tile_info.cpu; 561 struct hantro_dev *vpu = ctx->dev; 562 int tile0, tile1; 563 564 memset(dst, 0, av1_dec->tile_info.size); 565 566 for (tile0 = 0; tile0 < tile_info.tile_cols; tile0++) { 567 for (tile1 = 0; tile1 < tile_info.tile_rows; tile1++) { 568 int tile_id = tile1 * tile_info.tile_cols + tile0; 569 uint32_t start, end; 570 uint32_t y0 = 571 tile_info.height_in_sbs_minus_1[tile1] + 1; 572 uint32_t x0 = tile_info.width_in_sbs_minus_1[tile0] + 1; 573 574 // tile size in SB units (width,height) 575 *dst++ = x0; 576 *dst++ = 0; 577 *dst++ = 0; 578 *dst++ = 0; 579 *dst++ = y0; 580 *dst++ = 0; 581 *dst++ = 0; 582 *dst++ = 0; 583 584 // tile start position 585 start = group_entry[tile_id].tile_offset - group_entry[0].tile_offset; 586 *dst++ = start & 255; 587 *dst++ = (start >> 8) & 255; 588 *dst++ = (start >> 16) & 255; 589 *dst++ = (start >> 24) & 255; 590 591 // # of bytes in tile data 592 end = start + group_entry[tile_id].tile_size; 593 *dst++ = end & 255; 594 *dst++ = (end >> 8) & 255; 595 *dst++ = (end >> 16) & 255; 596 *dst++ = (end >> 24) & 255; 597 } 598 } 599 600 hantro_reg_write(vpu, &av1_multicore_expect_context_update, 601 !!(context_update_x == 0)); 602 hantro_reg_write(vpu, &av1_tile_enable, !!((tile_info.tile_cols > 1) 603 || (tile_info.tile_rows > 1))); 604 hantro_reg_write(vpu, &av1_num_tile_cols_8k, tile_info.tile_cols); 605 hantro_reg_write(vpu, &av1_num_tile_rows_8k, tile_info.tile_rows); 606 hantro_reg_write(vpu, &av1_context_update_tile_id, 607 context_update_tile_id); 608 hantro_reg_write(vpu, &av1_tile_transpose, 1); 609 if (context_update_tile_id) { 610 hantro_reg_write(vpu, &av1_dec_tile_size_mag, 611 tile_info.tile_size_bytes); 612 } else 613 hantro_reg_write(vpu, &av1_dec_tile_size_mag, 3); 614 615 hantro_write_addr(vpu, AV1_TILE_BASE, av1_dec->tile_info.dma); > 616 } 617 -- 0-DAY CI Kernel Test Service https://01.org/lkp