From: Rick Wertenbroek <rick.wertenbroek@gmail.com>
To: alberto.dassatti@heig-vd.ch
Cc: damien.lemoal@opensource.wdc.com, xxm@rock-chips.com,
"Rick Wertenbroek" <rick.wertenbroek@gmail.com>,
"Shawn Lin" <shawn.lin@rock-chips.com>,
"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
"Krzysztof Wilczyński" <kw@linux.com>,
"Rob Herring" <robh@kernel.org>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>,
"Heiko Stuebner" <heiko@sntech.de>,
"Johan Jonker" <jbx6244@gmail.com>,
"Brian Norris" <briannorris@chromium.org>,
"Caleb Connolly" <kc@postmarketos.org>,
"Corentin Labbe" <clabbe@baylibre.com>,
"Arnaud Ferraris" <arnaud.ferraris@collabora.com>,
"Lin Huang" <hl@rock-chips.com>,
"Judy Hsiao" <judyhsiao@chromium.org>,
"Hugh Cole-Baker" <sigmaris@gmail.com>,
linux-pci@vger.kernel.org, linux-rockchip@lists.infradead.org,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: [PATCH v3 10/11] PCI: rockchip: Don't advertise MSI-X in PCIe capabilities
Date: Tue, 4 Apr 2023 10:24:23 +0200 [thread overview]
Message-ID: <20230404082426.3880812-11-rick.wertenbroek@gmail.com> (raw)
In-Reply-To: <20230404082426.3880812-1-rick.wertenbroek@gmail.com>
The RK3399 PCIe endpoint controller cannot generate MSI-X IRQs.
This is documented in the RK3399 technical reference manual (TRM)
section 17.5.9 "Interrupt Support".
MSI-X capability should therefore not be advertised. Remove the
MSI-X capability by editing the capability linked-list. The
previous entry is the MSI capability, therefore get the next
entry from the MSI-X capability entry and set it as next entry
for the MSI capability. This in effect removes MSI-X from the list.
Linked list before : MSI cap -> MSI-X cap -> PCIe Device cap -> ...
Linked list now : MSI cap -> PCIe Device cap -> ...
Signed-off-by: Rick Wertenbroek <rick.wertenbroek@gmail.com>
---
drivers/pci/controller/pcie-rockchip-ep.c | 15 +++++++++++++++
drivers/pci/controller/pcie-rockchip.h | 5 +++++
2 files changed, 20 insertions(+)
diff --git a/drivers/pci/controller/pcie-rockchip-ep.c b/drivers/pci/controller/pcie-rockchip-ep.c
index 924b95bd736c..20c768287870 100644
--- a/drivers/pci/controller/pcie-rockchip-ep.c
+++ b/drivers/pci/controller/pcie-rockchip-ep.c
@@ -510,6 +510,7 @@ static int rockchip_pcie_ep_probe(struct platform_device *pdev)
size_t max_regions;
struct pci_epc_mem_window *windows = NULL;
int err, i;
+ u32 cfg_msi, cfg_msix_cp;
ep = devm_kzalloc(dev, sizeof(*ep), GFP_KERNEL);
if (!ep)
@@ -584,6 +585,20 @@ static int rockchip_pcie_ep_probe(struct platform_device *pdev)
ep->irq_pci_addr = ROCKCHIP_PCIE_EP_DUMMY_IRQ_ADDR;
+ cfg_msi = rockchip_pcie_read(rockchip, PCIE_EP_CONFIG_BASE +
+ ROCKCHIP_PCIE_EP_MSI_CTRL_REG);
+
+ cfg_msi &= ~ROCKCHIP_PCIE_EP_MSI_CP1_MASK;
+
+ cfg_msix_cp = rockchip_pcie_read(rockchip, PCIE_EP_CONFIG_BASE +
+ ROCKCHIP_PCIE_EP_MSIX_CAP_REG) &
+ ROCKCHIP_PCIE_EP_MSIX_CAP_CP_MASK;
+
+ cfg_msi |= cfg_msix_cp;
+
+ rockchip_pcie_write(rockchip, cfg_msi,
+ PCIE_EP_CONFIG_BASE + ROCKCHIP_PCIE_EP_MSI_CTRL_REG);
+
rockchip_pcie_write(rockchip, PCIE_CLIENT_CONF_ENABLE, PCIE_CLIENT_CONFIG);
return 0;
diff --git a/drivers/pci/controller/pcie-rockchip.h b/drivers/pci/controller/pcie-rockchip.h
index 1558eae298ae..a21070ea7166 100644
--- a/drivers/pci/controller/pcie-rockchip.h
+++ b/drivers/pci/controller/pcie-rockchip.h
@@ -226,6 +226,8 @@
#define ROCKCHIP_PCIE_EP_CMD_STATUS 0x4
#define ROCKCHIP_PCIE_EP_CMD_STATUS_IS BIT(19)
#define ROCKCHIP_PCIE_EP_MSI_CTRL_REG 0x90
+#define ROCKCHIP_PCIE_EP_MSI_CP1_OFFSET 8
+#define ROCKCHIP_PCIE_EP_MSI_CP1_MASK GENMASK(15, 8)
#define ROCKCHIP_PCIE_EP_MSI_FLAGS_OFFSET 16
#define ROCKCHIP_PCIE_EP_MSI_CTRL_MMC_OFFSET 17
#define ROCKCHIP_PCIE_EP_MSI_CTRL_MMC_MASK GENMASK(19, 17)
@@ -233,6 +235,9 @@
#define ROCKCHIP_PCIE_EP_MSI_CTRL_MME_MASK GENMASK(22, 20)
#define ROCKCHIP_PCIE_EP_MSI_CTRL_ME BIT(16)
#define ROCKCHIP_PCIE_EP_MSI_CTRL_MASK_MSI_CAP BIT(24)
+#define ROCKCHIP_PCIE_EP_MSIX_CAP_REG 0xb0
+#define ROCKCHIP_PCIE_EP_MSIX_CAP_CP_OFFSET 8
+#define ROCKCHIP_PCIE_EP_MSIX_CAP_CP_MASK GENMASK(15, 8)
#define ROCKCHIP_PCIE_EP_DUMMY_IRQ_ADDR 0x1
#define ROCKCHIP_PCIE_EP_PCI_LEGACY_IRQ_ADDR 0x3
#define ROCKCHIP_PCIE_EP_FUNC_BASE(fn) \
--
2.25.1
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
next prev parent reply other threads:[~2023-04-04 8:48 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-04 8:24 [PATCH v3 00/11] PCI: rockchip: Fix RK3399 PCIe endpoint controller driver Rick Wertenbroek
2023-04-04 8:24 ` [PATCH v3 01/11] PCI: rockchip: Remove writes to unused registers Rick Wertenbroek
2023-04-04 8:24 ` [PATCH v3 02/11] PCI: rockchip: Write PCI Device ID to correct register Rick Wertenbroek
2023-04-04 8:24 ` [PATCH v3 03/11] PCI: rockchip: Assert PCI Configuration Enable bit after probe Rick Wertenbroek
2023-04-04 8:24 ` [PATCH v3 04/11] PCI: rockchip: Add poll and timeout to wait for PHY PLLs to be locked Rick Wertenbroek
2023-04-04 8:24 ` [PATCH v3 05/11] arm64: dts: rockchip: Add dtsi entry for RK3399 PCIe endpoint core Rick Wertenbroek
2023-04-04 8:24 ` [PATCH v3 06/11] dt-bindings: PCI: Update the RK3399 example to a valid one Rick Wertenbroek
2023-04-04 8:45 ` Krzysztof Kozlowski
2023-04-04 8:58 ` Rick Wertenbroek
2023-04-04 13:29 ` Krzysztof Kozlowski
2023-04-04 14:42 ` Rick Wertenbroek
2023-04-04 8:24 ` [PATCH v3 07/11] PCI: rockchip: Fix legacy IRQ generation for RK3399 PCIe endpoint core Rick Wertenbroek
2023-04-04 8:24 ` [PATCH v3 08/11] PCI: rockchip: Fix window mapping and address translation for endpoint Rick Wertenbroek
2023-04-05 11:43 ` Damien Le Moal
2023-04-04 8:24 ` [PATCH v3 09/11] PCI: rockchip: Use u32 variable to access 32-bit registers Rick Wertenbroek
2023-04-04 8:24 ` Rick Wertenbroek [this message]
2023-04-05 11:50 ` [PATCH v3 10/11] PCI: rockchip: Don't advertise MSI-X in PCIe capabilities Damien Le Moal
2023-04-04 8:24 ` [PATCH v3 11/11] PCI: rockchip: Set address alignment for endpoint mode Rick Wertenbroek
2023-04-05 9:23 ` [PATCH v3 00/11] PCI: rockchip: Fix RK3399 PCIe endpoint controller driver Damien Le Moal
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20230404082426.3880812-11-rick.wertenbroek@gmail.com \
--to=rick.wertenbroek@gmail.com \
--cc=alberto.dassatti@heig-vd.ch \
--cc=arnaud.ferraris@collabora.com \
--cc=bhelgaas@google.com \
--cc=briannorris@chromium.org \
--cc=clabbe@baylibre.com \
--cc=damien.lemoal@opensource.wdc.com \
--cc=devicetree@vger.kernel.org \
--cc=heiko@sntech.de \
--cc=hl@rock-chips.com \
--cc=jbx6244@gmail.com \
--cc=judyhsiao@chromium.org \
--cc=kc@postmarketos.org \
--cc=krzysztof.kozlowski+dt@linaro.org \
--cc=kw@linux.com \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pci@vger.kernel.org \
--cc=linux-rockchip@lists.infradead.org \
--cc=lpieralisi@kernel.org \
--cc=robh@kernel.org \
--cc=shawn.lin@rock-chips.com \
--cc=sigmaris@gmail.com \
--cc=xxm@rock-chips.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox