From: Jagan Teki <jagan@edgeble.ai>
To: Heiko Stuebner <heiko@sntech.de>,
linux-arm-kernel@lists.infradead.org,
linux-rockchip@lists.infradead.org
Cc: Jagan Teki <jagan@edgeble.ai>,
linux-clk@vger.kernel.org,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>
Subject: [PATCH 02/14] clk: rockchip: rv1126: Add PD_VO clock tree
Date: Mon, 31 Jul 2023 16:30:00 +0530 [thread overview]
Message-ID: <20230731110012.2913742-3-jagan@edgeble.ai> (raw)
In-Reply-To: <20230731110012.2913742-1-jagan@edgeble.ai>
PD_VO clock tree diagram in RV1126 is connected to
- BIU_VO
- VOP
- RGA
- IEP
- DSIHOST
Add entire PD_VO clock tree for rv1126.
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
---
Cc: linux-clk@vger.kernel.org
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.org>
drivers/clk/rockchip/clk-rv1126.c | 59 +++++++++++++++++++++++++++++++
1 file changed, 59 insertions(+)
diff --git a/drivers/clk/rockchip/clk-rv1126.c b/drivers/clk/rockchip/clk-rv1126.c
index 5c6f1ce34a2f..fc19c5522490 100644
--- a/drivers/clk/rockchip/clk-rv1126.c
+++ b/drivers/clk/rockchip/clk-rv1126.c
@@ -175,6 +175,7 @@ PNAME(mux_i2s2_p) = { "mclk_i2s2_div", "mclk_i2s2_fracdiv", "i2s2_mclkin", "xi
PNAME(mux_i2s2_out2io_p) = { "mclk_i2s2", "xin12m" };
PNAME(mux_gpll_cpll_xin24m_p) = { "gpll", "cpll", "xin24m" };
PNAME(mux_audpwm_p) = { "sclk_audpwm_div", "sclk_audpwm_fracdiv", "xin24m" };
+PNAME(mux_dclk_vop_p) = { "dclk_vop_div", "dclk_vop_fracdiv", "xin24m" };
PNAME(mux_usb480m_gpll_p) = { "usb480m", "gpll" };
PNAME(clk_gmac_src_m0_p) = { "clk_gmac_div", "clk_gmac_rgmii_m0" };
PNAME(clk_gmac_src_m1_p) = { "clk_gmac_div", "clk_gmac_rgmii_m1" };
@@ -259,6 +260,10 @@ static struct rockchip_clk_branch rv1126_audpwm_fracmux __initdata =
MUX(SCLK_AUDPWM_MUX, "mclk_audpwm_mux", mux_audpwm_p, CLK_SET_RATE_PARENT,
RV1126_CLKSEL_CON(36), 8, 2, MFLAGS);
+static struct rockchip_clk_branch rv1126_dclk_vop_fracmux __initdata =
+ MUX(DCLK_VOP_MUX, "dclk_vop_mux", mux_dclk_vop_p, CLK_SET_RATE_PARENT,
+ RV1126_CLKSEL_CON(47), 10, 2, MFLAGS);
+
static struct rockchip_clk_branch rv1126_clk_pmu_branches[] __initdata = {
/*
* Clock-Architecture Diagram 2
@@ -714,6 +719,49 @@ static struct rockchip_clk_branch rv1126_clk_branches[] __initdata = {
RV1126_CLKSEL_CON(72), 8, 1, MFLAGS, 0, 7, DFLAGS,
RV1126_CLKGATE_CON(11), 1, GFLAGS),
+ /*
+ * Clock-Architecture Diagram 9
+ */
+ /* PD_VO */
+ COMPOSITE(ACLK_PDVO, "aclk_pdvo", mux_gpll_cpll_p, 0,
+ RV1126_CLKSEL_CON(45), 7, 1, MFLAGS, 0, 5, DFLAGS,
+ RV1126_CLKGATE_CON(14), 0, GFLAGS),
+ COMPOSITE_NOMUX(HCLK_PDVO, "hclk_pdvo", "aclk_pdvo", 0,
+ RV1126_CLKSEL_CON(45), 8, 5, DFLAGS,
+ RV1126_CLKGATE_CON(14), 1, GFLAGS),
+ COMPOSITE_NOMUX(PCLK_PDVO, "pclk_pdvo", "aclk_pdvo", 0,
+ RV1126_CLKSEL_CON(46), 8, 5, DFLAGS,
+ RV1126_CLKGATE_CON(14), 2, GFLAGS),
+ GATE(ACLK_RGA, "aclk_rga", "aclk_pdvo", 0,
+ RV1126_CLKGATE_CON(14), 6, GFLAGS),
+ GATE(HCLK_RGA, "hclk_rga", "hclk_pdvo", 0,
+ RV1126_CLKGATE_CON(14), 7, GFLAGS),
+ COMPOSITE(CLK_RGA_CORE, "clk_rga_core", mux_gpll_cpll_p, 0,
+ RV1126_CLKSEL_CON(46), 7, 1, MFLAGS, 0, 5, DFLAGS,
+ RV1126_CLKGATE_CON(14), 8, GFLAGS),
+ GATE(ACLK_VOP, "aclk_vop", "aclk_pdvo", 0,
+ RV1126_CLKGATE_CON(14), 9, GFLAGS),
+ GATE(HCLK_VOP, "hclk_vop", "hclk_pdvo", 0,
+ RV1126_CLKGATE_CON(14), 10, GFLAGS),
+ COMPOSITE(DCLK_VOP_DIV, "dclk_vop_div", mux_gpll_cpll_p, 0,
+ RV1126_CLKSEL_CON(47), 8, 1, MFLAGS, 0, 8, DFLAGS,
+ RV1126_CLKGATE_CON(14), 11, GFLAGS),
+ COMPOSITE_FRACMUX(DCLK_VOP_FRACDIV, "dclk_vop_fracdiv", "dclk_vop_div",
+ CLK_SET_RATE_PARENT, RV1126_CLKSEL_CON(48), 0,
+ RV1126_CLKGATE_CON(14), 12, GFLAGS,
+ &rv1126_dclk_vop_fracmux),
+ GATE(DCLK_VOP, "dclk_vop", "dclk_vop_mux", 0,
+ RV1126_CLKGATE_CON(14), 13, GFLAGS),
+ GATE(PCLK_DSIHOST, "pclk_dsihost", "pclk_pdvo", 0,
+ RV1126_CLKGATE_CON(14), 14, GFLAGS),
+ GATE(ACLK_IEP, "aclk_iep", "aclk_pdvo", 0,
+ RV1126_CLKGATE_CON(12), 7, GFLAGS),
+ GATE(HCLK_IEP, "hclk_iep", "hclk_pdvo", 0,
+ RV1126_CLKGATE_CON(12), 8, GFLAGS),
+ COMPOSITE(CLK_IEP_CORE, "clk_iep_core", mux_gpll_cpll_p, 0,
+ RV1126_CLKSEL_CON(54), 7, 1, MFLAGS, 0, 5, DFLAGS,
+ RV1126_CLKGATE_CON(12), 9, GFLAGS),
+
/*
* Clock-Architecture Diagram 12
*/
@@ -905,6 +953,17 @@ static struct rockchip_clk_branch rv1126_clk_branches[] __initdata = {
GATE(0, "pclk_pdaudio_niu", "hclk_pdaudio", CLK_IGNORE_UNUSED,
RV1126_CLKGATE_CON(9), 3, GFLAGS),
+ /*
+ * Clock-Architecture Diagram 9
+ */
+ /* PD_VO */
+ GATE(0, "aclk_pdvo_niu", "aclk_pdvo", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(14), 3, GFLAGS),
+ GATE(0, "hclk_pdvo_niu", "hclk_pdvo", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(14), 4, GFLAGS),
+ GATE(0, "pclk_pdvo_niu", "pclk_pdvo", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(14), 5, GFLAGS),
+
/*
* Clock-Architecture Diagram 12
*/
--
2.25.1
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next prev parent reply other threads:[~2023-07-31 11:00 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-31 10:59 [PATCH 00/14] drm: rockchip: Add RV1126 Display (MIPI DSI) support Jagan Teki
2023-07-31 10:59 ` [PATCH 01/14] genpd: rockchip: Add PD_VO entry for rv1126 Jagan Teki
2023-07-31 20:48 ` Heiko Stübner
2023-08-12 12:57 ` Heiko Stübner
2023-08-14 11:45 ` Ulf Hansson
2023-07-31 11:00 ` Jagan Teki [this message]
2023-07-31 11:00 ` [PATCH 03/14] dt-bindings: phy: rockchip-inno-dsidphy: Document rv1126 Jagan Teki
2023-07-31 20:49 ` Heiko Stübner
2023-08-11 17:52 ` Rob Herring
2023-07-31 11:00 ` [PATCH 04/14] phy: rockchip: inno-dsidphy: Add rv1126 support Jagan Teki
2023-07-31 20:49 ` Heiko Stübner
2023-07-31 11:00 ` [PATCH 05/14] dt-bindings: display: rockchip-vop: Document rv1126 vop Jagan Teki
2023-08-01 21:07 ` Conor Dooley
2023-08-02 14:37 ` Jagan Teki
2023-08-02 15:12 ` Conor Dooley
2023-07-31 11:00 ` [PATCH 06/14] drm/rockchip: vop: Add rv1126 vop_lite support Jagan Teki
2023-07-31 11:00 ` [PATCH 07/14] dt-bindings: display: rockchip-dw-mipi-dsi: Document rv1126 DSI Jagan Teki
2023-08-01 21:05 ` Conor Dooley
2023-07-31 11:00 ` [PATCH 08/14] drm/rockchip: dsi: Add rv1126 MIPI DSI support Jagan Teki
2023-07-31 11:00 ` [PATCH 09/14] ARM: dts: rockchip: rv1126: Add PD_VO entry Jagan Teki
2023-07-31 11:00 ` [PATCH 10/14] ARM: dts: rockchip: rv1126: Add VOP_LITE support Jagan Teki
2023-07-31 11:00 ` [PATCH 11/14] ARM: dts: rockchip: rv1126: Add MIPI DSI pipeline Jagan Teki
2023-07-31 11:00 ` [PATCH 12/14] ARM: dts: rockchip: rv1126: Add Edgeble Neu2 IO DSI overlay Jagan Teki
2023-07-31 11:00 ` [PATCH 13/14] ARM: dts: rockchip: Add Radxa Display 10HD overlay Jagan Teki
2023-07-31 11:00 ` [PATCH 14/14] ARM: dts: rockchip: Add Radxa Display 8HD overlay Jagan Teki
2023-08-10 21:08 ` (subset) [PATCH 00/14] drm: rockchip: Add RV1126 Display (MIPI DSI) support Heiko Stuebner
2023-08-10 21:28 ` Heiko Stuebner
2023-08-12 12:54 ` Heiko Stuebner
2023-08-12 13:00 ` Heiko Stuebner
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