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boundary="===============0353808229470222827==" Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org --===============0353808229470222827== Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="BqjkFo/XhTGy7ekD" Content-Disposition: inline --BqjkFo/XhTGy7ekD Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Mon, Aug 19, 2024 at 01:29:30AM +0300, Cristian Ciocaltea wrote: > Rockchip RK3588 SoC integrates the Synopsys DesignWare HDMI 2.1 > Quad-Pixel (QP) TX controller IP. >=20 > Since this is a new IP block, quite different from those used in the > previous generations of Rockchip SoCs, add a dedicated binding file. >=20 > Signed-off-by: Cristian Ciocaltea > --- > .../display/rockchip/rockchip,dw-hdmi-qp.yaml | 170 +++++++++++++++= ++++++ > 1 file changed, 170 insertions(+) >=20 > diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip,= dw-hdmi-qp.yaml b/Documentation/devicetree/bindings/display/rockchip/rockch= ip,dw-hdmi-qp.yaml > new file mode 100644 > index 000000000000..de470923d823 > --- /dev/null > +++ b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi= -qp.yaml Filename matching the compatible please. > @@ -0,0 +1,170 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/display/rockchip/rockchip,dw-hdmi-qp.= yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Rockchip DW HDMI QP TX Encoder > + > +maintainers: > + - Cristian Ciocaltea > + > +description: > + Rockchip RK3588 SoC integrates the Synopsys DesignWare HDMI QP TX cont= roller > + IP and a HDMI/eDP TX Combo PHY based on a Samsung IP block. > + > +allOf: > + - $ref: /schemas/display/bridge/synopsys,dw-hdmi-qp.yaml# > + - $ref: /schemas/sound/dai-common.yaml# > + > +properties: > + compatible: > + enum: > + - rockchip,rk3588-dw-hdmi-qp > + > + clocks: > + minItems: 4 > + items: > + - {} > + - {} > + - {} > + - {} Why have you chosen to do things like this? I find it makes things less clear than reiterating the names of the required clocks. > + # The next clocks are optional, but shall be specified in this > + # order when present. > + - description: TMDS/FRL link clock > + - description: Video datapath clock I don't get what you mean by optional. You have one SoC, either they are or are not connected, unless there's multiple instances of this IP block on the SoC and some do and some do not have these clocks? Ditto for the interrupts. > + > + clock-names: > + minItems: 4 > + items: > + - {} > + - {} > + - {} > + - {} > + - enum: [hdp, hclk_vo1] > + - const: hclk_vo1 > + > + interrupts: > + items: > + - {} > + - {} > + - {} > + - {} > + - description: HPD interrupt > + > + interrupt-names: > + items: > + - {} > + - {} > + - {} > + - {} > + - const: hpd > + > + phys: > + maxItems: 1 > + description: The HDMI/eDP PHY. > + > + phy-names: > + const: hdmi > + > + power-domains: > + maxItems: 1 > + > + resets: > + minItems: 2 > + maxItems: 2 > + > + reset-names: > + items: > + - const: ref > + - const: hdp > + > + "#sound-dai-cells": > + const: 0 > + > + rockchip,grf: > + $ref: /schemas/types.yaml#/definitions/phandle > + description: > + Most HDMI QP related data is accessed through SYS GRF regs. > + > + rockchip,vo1-grf: > + $ref: /schemas/types.yaml#/definitions/phandle > + description: > + Additional HDMI QP related data is accessed through VO1 GRF regs. Why are these required? What prevents you looking up the syscons by compatible? Cheers, Conor. > + > +required: > + - compatible > + - reg > + - clocks > + - clock-names > + - interrupts > + - interrupt-names > + - phys > + - phy-names > + - ports > + - resets > + - reset-names > + - rockchip,grf > + - rockchip,vo1-grf > + > +unevaluatedProperties: false > + > +examples: > + - | > + #include > + #include > + #include > + #include > + #include > + > + soc { > + #address-cells =3D <2>; > + #size-cells =3D <2>; > + > + hdmi@fde80000 { > + compatible =3D "rockchip,rk3588-dw-hdmi-qp"; > + reg =3D <0x0 0xfde80000 0x0 0x20000>; > + clocks =3D <&cru PCLK_HDMITX0>, > + <&cru CLK_HDMITX0_EARC>, > + <&cru CLK_HDMITX0_REF>, > + <&cru MCLK_I2S5_8CH_TX>, > + <&cru CLK_HDMIHDP0>, > + <&cru HCLK_VO1>; > + clock-names =3D "pclk", "earc", "ref", "aud", "hdp", "hclk_vo1"; > + interrupts =3D , > + , > + , > + , > + ; > + interrupt-names =3D "avp", "cec", "earc", "main", "hpd"; > + phys =3D <&hdptxphy_hdmi0>; > + phy-names =3D "hdmi"; > + power-domains =3D <&power RK3588_PD_VO1>; > + resets =3D <&cru SRST_HDMITX0_REF>, <&cru SRST_HDMIHDP0>; > + reset-names =3D "ref", "hdp"; > + rockchip,grf =3D <&sys_grf>; > + rockchip,vo1-grf =3D <&vo1_grf>; > + #sound-dai-cells =3D <0>; > + > + ports { > + #address-cells =3D <1>; > + #size-cells =3D <0>; > + > + port@0 { > + reg =3D <0>; > + > + hdmi0_in_vp0: endpoint { > + remote-endpoint =3D <&vp0_out_hdmi0>; > + }; > + }; > + > + port@1 { > + reg =3D <1>; > + > + hdmi0_out_con0: endpoint { > + remote-endpoint =3D <&hdmi_con0_in>; > + }; > + }; > + }; > + }; > + }; >=20 > --=20 > 2.46.0 >=20 --BqjkFo/XhTGy7ekD Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQRh246EGq/8RLhDjO14tDGHoIJi0gUCZsN4lwAKCRB4tDGHoIJi 0uMlAQCeNiyUGCxDpjROAQ54l9m7hMljsdP2KRn6KVEBgpgwhAD/S9KJnlaANagj HTaIDomg1UIgte88LE7zDjLZYOJmWgo= =uaDs -----END PGP SIGNATURE----- --BqjkFo/XhTGy7ekD-- --===============0353808229470222827== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip --===============0353808229470222827==--