Re: [PATCH v3 1/2] dt-bindings: phy: Add Rockchip MIPI CSI/DSI PHY schema

Sebastian Reichel
2024-11-22T18:50:39Z

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Hi,

On Wed, Nov 13, 2024 at 11:10:17PM +0100, Heiko Stuebner wrote:
> From: Heiko Stuebner <heiko.stuebner@cherry.de>
>
> Add dt-binding schema for the MIPI CSI/DSI PHY found on
> Rockchip RK3588 SoCs.
>
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> Signed-off-by: Heiko Stuebner <heiko.stuebner@cherry.de>
> ---
> .../phy/rockchip,rk3588-mipi-dcphy.yaml | 82 +++++++++++++++++++
> 1 file changed, 82 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/phy/rockchip,rk3588-mipi-dcphy.yaml
>
> diff --git a/Documentation/devicetree/bindings/phy/rockchip,rk3588-mipi-dcphy.yaml b/Documentation/devicetree/bindings/phy/rockchip,rk3588-mipi-dcphy.yaml
> new file mode 100644
> index 000000000000..5ee8d7246fa0
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/rockchip,rk3588-mipi-dcphy.yaml
> @@ -0,0 +1,82 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/phy/rockchip,rk3588-mipi-dcphy.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Rockchip MIPI CSI/DSI PHY with Samsung IP block
> +
> +maintainers:
> + - Guochun Huang <hero.huang@rock-chips.com>
> + - Heiko Stuebner <heiko@sntech.de>
> +
> +properties:
> + compatible:
> + enum:
> + - rockchip,rk3576-mipi-dcphy
> + - rockchip,rk3588-mipi-dcphy
> +
> + reg:
> + maxItems: 1
> +
> + "#phy-cells":
> + const: 0

I would expect an argument to select between D-PHY and C-PHY mode,
so that the binding is ready for it even when the driver does not
yet support it. E.g. something like

'#phy-cells':
const: 1
description: |
Supported modes are:
- PHY_TYPE_DPHY
- PHY_TYPE_CPHY
See include/dt-bindings/phy/phy.h for constants.

This would match how it works for the naneng Combo PHY to switch
between PCIe/SATA/USB3. Also Mediatek CSI DC-PHY handles it that
way upstream (with just D-PHY being supported). I see that the
driver stack you send upstream expects, that the PHY user (e.g.
the DSI controller) instead manually calls phy_set_mode(phy, <mode>).
To me it seems more sensible to just get this automaically from DT.

Otherwise the whole series LGTM.

Greetings,

-- Sebastian

> + clocks:
> + maxItems: 2
> +
> + clock-names:
> + items:
> + - const: pclk
> + - const: ref
> +
> + resets:
> + maxItems: 4
> +
> + reset-names:
> + items:
> + - const: m_phy
> + - const: apb
> + - const: grf
> + - const: s_phy
> +
> + rockchip,grf:
> + $ref: /schemas/types.yaml#/definitions/phandle
> + description:
> + Phandle to the syscon managing the 'mipi dcphy general register files'.
> +
> +required:
> + - compatible
> + - reg
> + - clocks
> + - clock-names
> + - resets
> + - reset-names
> + - "#phy-cells"
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/rockchip,rk3588-cru.h>
> + #include <dt-bindings/reset/rockchip,rk3588-cru.h>
> +
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + phy@feda0000 {
> + compatible = "rockchip,rk3588-mipi-dcphy";
> + reg = <0x0 0xfeda0000 0x0 0x10000>;
> + clocks = <&cru PCLK_MIPI_DCPHY0>,
> + <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>;
> + clock-names = "pclk", "ref";
> + resets = <&cru SRST_M_MIPI_DCPHY0>,
> + <&cru SRST_P_MIPI_DCPHY0>,
> + <&cru SRST_P_MIPI_DCPHY0_GRF>,
> + <&cru SRST_S_MIPI_DCPHY0>;
> + reset-names = "m_phy", "apb", "grf", "s_phy";
> + rockchip,grf = <&mipidcphy0_grf>;
> + #phy-cells = <0>;
> + };
> + };
> --
> 2.45.2
>
>

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