From: Val Packett <val@packett.cool>
Cc: Val Packett <val@packett.cool>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>, Heiko Stuebner <heiko@sntech.de>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org
Subject: [PATCH v2 2/2] clk: rockchip: use PCLK_CIF0/1 clock IDs on RK3066
Date: Thu, 5 Dec 2024 15:29:36 -0300 [thread overview]
Message-ID: <20241205182954.5346-2-val@packett.cool> (raw)
In-Reply-To: <20241205182954.5346-1-val@packett.cool>
RK3066 has two "CIF" video capture interface blocks, reference the
newly added IDs for their PCLK clocks.
Signed-off-by: Val Packett <val@packett.cool>
---
drivers/clk/rockchip/clk-rk3188.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/rockchip/clk-rk3188.c b/drivers/clk/rockchip/clk-rk3188.c
index 684233e72105..81e94b338d0f 100644
--- a/drivers/clk/rockchip/clk-rk3188.c
+++ b/drivers/clk/rockchip/clk-rk3188.c
@@ -344,7 +344,7 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = {
GATE(0, "pclkin_cif0", "ext_cif0", 0,
RK2928_CLKGATE_CON(3), 3, GFLAGS),
- INVERTER(0, "pclk_cif0", "pclkin_cif0",
+ INVERTER(PCLK_CIF0, "pclk_cif0", "pclkin_cif0",
RK2928_CLKSEL_CON(30), 8, IFLAGS),
FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
@@ -602,7 +602,7 @@ static struct rockchip_clk_branch rk3066a_clk_branches[] __initdata = {
GATE(0, "pclkin_cif1", "ext_cif1", 0,
RK2928_CLKGATE_CON(3), 4, GFLAGS),
- INVERTER(0, "pclk_cif1", "pclkin_cif1",
+ INVERTER(PCLK_CIF1, "pclk_cif1", "pclkin_cif1",
RK2928_CLKSEL_CON(30), 12, IFLAGS),
COMPOSITE(0, "aclk_gpu_src", mux_pll_src_cpll_gpll_p, 0,
--
2.47.1
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next prev parent reply other threads:[~2024-12-05 18:33 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-12-05 18:29 [PATCH v2 1/2] dt-bindings: clock: rk3188-common: add PCLK_CIF0/PCLK_CIF1 Val Packett
2024-12-05 18:29 ` Val Packett [this message]
2024-12-06 17:08 ` Conor Dooley
2025-02-10 11:02 ` Heiko Stuebner
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