[PATCH v5 05/12] arm64: dts: rockchip: Add properties for pcie2x1l2 for Radxa ROCK 5C

FUKAUMI Naoki
2024-12-16T12:39:56Z

By schematic[1], pcie2x1l2 CLKREQ and WAKE pins are connected.
Describe them in dts.

[1] https://dl.radxa.com/rock5/5c/docs/hw/v1100/radxa_rock_5c_schematic_v1100.pdf

Fixes: 3ddf5cdb77e6 ("arm64: dts: rockchip: add Radxa ROCK 5C")
Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
---
Changes in v5:
- Reword commit message
Changes in v4:
- none
Changes in v3:
- none
Changes in v2:
- reword commit message
---
arch/arm64/boot/dts/rockchip/rk3588s-rock-5c.dts | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5c.dts b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5c.dts
index 61d75ab503b2..01537b47f880 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5c.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5c.dts
@@ -419,7 +419,9 @@ rgmii_phy1: ethernet-phy@1 {

&pcie2x1l2 {
pinctrl-names = "default";
- pinctrl-0 = <&pcie20x1_2_perstn_m0>;
+ pinctrl-0 = <&pcie20x1_2_perstn_m0>,
+ <&pcie20x1m0_clkreqn>,
+ <&pcie20x1m0_waken>;
reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>;
vpcie3v3-supply = <&vcc3v3_pcie2x1l2>;
status = "okay";
--
2.43.0