[PATCH v3 0/6] PCI: endpoint: Add support for resizable BARs

[PATCH v3 0/6] PCI: endpoint: Add support for resizable BARs

[Niklas Cassel]

The PCI endpoint framework currently does not support resizable BARs.

Add a new BAR type BAR_RESIZABLE, so that EPC drivers can support resizable
BARs properly.

For a resizable BAR, we will only allow a single supported size.
This is by design, as we do not need/want the complexity of the host side
resizing our resizable BAR.

In the DWC driver specifically, the DWC driver currently handles resizable
BARs using an ugly hack where a resizable BAR is force set to a fixed size
BAR with 1 MB size if detected. This is bogus, as a resizable BAR can be
configured to sizes other than 1 MB.

With these changes, an EPF driver will be able to call pci_epc_set_bar()
to configure a resizable BAR to an arbitrary size, just like for
BAR_PROGRAMMABLE. Thus, DWC based EPF drivers will no longer be forced to
a bogus 1 MB forced size for resizable BARs.


Tested/verified on a Radxa Rock 5b (rk3588) by:
-Modifying pci-epf-test.c to request BAR sizes that are larger than 1 MB:
 -static size_t bar_size[] = { 512, 512, 1024, 16384, 131072, 1048576 };
 +static size_t bar_size[] = { SZ_1M, SZ_1M, SZ_2M, SZ_2M, SZ_4M, SZ_4M };
 (Make sure to set CONFIG_CMA_ALIGNMENT=10 such that dma_alloc_coherent()
  calls are aligned even for allocations larger than 1 MB.)
-Rebooting the host to make sure that the DWC EP driver configures the BARs
 correctly after receiving a link down event.
-Modifying EPC features to configure a BAR as 64-bit, to make sure that we
 handle 64-bit BARs correctly.
-Modifying the DWC EP driver to set a size larger than 2 GB, to make sure
 we handle BAR sizes larger than 2 GB (for 64-bit BARs) correctly.
-Running the consecutive BAR test in pci_endpoint_test.c to make sure that
 the address translation works correctly.


Texas Instruments kernel developers, if would be very nice if you could
help out with testing on Keystone.


Changes since V2:
-When looping in dw_pcie_ep_init_non_sticky_registers(), use the index
 that we read from PCI_REBAR_CTRL (e.g. a platform could have BARs 0-2
 as programmable, and BARs 3-5 resizable, so we need to read the index).


Kind regards,
Niklas

Niklas Cassel (6):
  PCI: endpoint: Add BAR type BAR_RESIZABLE
  PCI: dwc: ep: Move dw_pcie_ep_find_ext_capability()
  PCI: dwc: endpoint: Add support for BAR type BAR_RESIZABLE
  PCI: keystone: Describe resizable BARs as resizable BARs
  PCI: keystone: Specify correct alignment requirement
  PCI: dw-rockchip: Describe resizable BARs as resizable BARs

 drivers/pci/controller/dwc/pci-keystone.c     |   6 +-
 .../pci/controller/dwc/pcie-designware-ep.c   | 231 +++++++++++++++---
 drivers/pci/controller/dwc/pcie-dw-rockchip.c |  22 +-
 drivers/pci/endpoint/pci-epf-core.c           |   4 +
 include/linux/pci-epc.h                       |   3 +
 5 files changed, 219 insertions(+), 47 deletions(-)

-- 
2.47.1


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[PATCH v3 6/6] PCI: dw-rockchip: Describe resizable BARs as resizable BARs

[Niklas Cassel]

Looking at "11.4.4.29 USP_PCIE_RESBAR Registers Summary" in the rk3588 TRM,
we can see that none of the BARs are Fixed BARs, but actually Resizable
BARs.

I couldn't find any reference in the rk3568 TRM, but looking at the
downstream PCIe endpoint driver, rk3568 and rk3588 are treated as the same,
so the BARs on rk3568 must also be Resizable BARs.

Now when we actually have support for Resizable BARs, let's configure
these BARs as such.

Signed-off-by: Niklas Cassel <cassel@kernel.org>
---
 drivers/pci/controller/dwc/pcie-dw-rockchip.c | 22 +++++++++----------
 1 file changed, 11 insertions(+), 11 deletions(-)

diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
index ce4b511bff9b..6a307a961756 100644
--- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c
+++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
@@ -273,12 +273,12 @@ static const struct pci_epc_features rockchip_pcie_epc_features_rk3568 = {
 	.msi_capable = true,
 	.msix_capable = true,
 	.align = SZ_64K,
-	.bar[BAR_0] = { .type = BAR_FIXED, .fixed_size = SZ_1M, },
-	.bar[BAR_1] = { .type = BAR_FIXED, .fixed_size = SZ_1M, },
-	.bar[BAR_2] = { .type = BAR_FIXED, .fixed_size = SZ_1M, },
-	.bar[BAR_3] = { .type = BAR_FIXED, .fixed_size = SZ_1M, },
-	.bar[BAR_4] = { .type = BAR_FIXED, .fixed_size = SZ_1M, },
-	.bar[BAR_5] = { .type = BAR_FIXED, .fixed_size = SZ_1M, },
+	.bar[BAR_0] = { .type = BAR_RESIZABLE, },
+	.bar[BAR_1] = { .type = BAR_RESIZABLE, },
+	.bar[BAR_2] = { .type = BAR_RESIZABLE, },
+	.bar[BAR_3] = { .type = BAR_RESIZABLE, },
+	.bar[BAR_4] = { .type = BAR_RESIZABLE, },
+	.bar[BAR_5] = { .type = BAR_RESIZABLE, },
 };
 
 /*
@@ -293,12 +293,12 @@ static const struct pci_epc_features rockchip_pcie_epc_features_rk3588 = {
 	.msi_capable = true,
 	.msix_capable = true,
 	.align = SZ_64K,
-	.bar[BAR_0] = { .type = BAR_FIXED, .fixed_size = SZ_1M, },
-	.bar[BAR_1] = { .type = BAR_FIXED, .fixed_size = SZ_1M, },
-	.bar[BAR_2] = { .type = BAR_FIXED, .fixed_size = SZ_1M, },
-	.bar[BAR_3] = { .type = BAR_FIXED, .fixed_size = SZ_1M, },
+	.bar[BAR_0] = { .type = BAR_RESIZABLE, },
+	.bar[BAR_1] = { .type = BAR_RESIZABLE, },
+	.bar[BAR_2] = { .type = BAR_RESIZABLE, },
+	.bar[BAR_3] = { .type = BAR_RESIZABLE, },
 	.bar[BAR_4] = { .type = BAR_RESERVED, },
-	.bar[BAR_5] = { .type = BAR_FIXED, .fixed_size = SZ_1M, },
+	.bar[BAR_5] = { .type = BAR_RESIZABLE, },
 };
 
 static const struct pci_epc_features *
-- 
2.47.1


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Re: [PATCH v3 0/6] PCI: endpoint: Add support for resizable BARs

[Manivannan Sadhasivam]

On Mon, Jan 13, 2025 at 11:27:31AM +0100, Niklas Cassel wrote:
> The PCI endpoint framework currently does not support resizable BARs.
> 
> Add a new BAR type BAR_RESIZABLE, so that EPC drivers can support resizable
> BARs properly.
> 
> For a resizable BAR, we will only allow a single supported size.
> This is by design, as we do not need/want the complexity of the host side
> resizing our resizable BAR.
> 
> In the DWC driver specifically, the DWC driver currently handles resizable
> BARs using an ugly hack where a resizable BAR is force set to a fixed size
> BAR with 1 MB size if detected. This is bogus, as a resizable BAR can be
> configured to sizes other than 1 MB.
> 
> With these changes, an EPF driver will be able to call pci_epc_set_bar()
> to configure a resizable BAR to an arbitrary size, just like for
> BAR_PROGRAMMABLE. Thus, DWC based EPF drivers will no longer be forced to
> a bogus 1 MB forced size for resizable BARs.
> 

The subject got me confused for a moment because, you are not really adding
support for Resizable BARs as per the PCIe spec, but just allowing the EPF
drivers to configure the size of the resizable BARs from fixed 1M. This is a
good improvement btw, but the subject should be reworded as such.

- Mani

> 
> Tested/verified on a Radxa Rock 5b (rk3588) by:
> -Modifying pci-epf-test.c to request BAR sizes that are larger than 1 MB:
>  -static size_t bar_size[] = { 512, 512, 1024, 16384, 131072, 1048576 };
>  +static size_t bar_size[] = { SZ_1M, SZ_1M, SZ_2M, SZ_2M, SZ_4M, SZ_4M };
>  (Make sure to set CONFIG_CMA_ALIGNMENT=10 such that dma_alloc_coherent()
>   calls are aligned even for allocations larger than 1 MB.)
> -Rebooting the host to make sure that the DWC EP driver configures the BARs
>  correctly after receiving a link down event.
> -Modifying EPC features to configure a BAR as 64-bit, to make sure that we
>  handle 64-bit BARs correctly.
> -Modifying the DWC EP driver to set a size larger than 2 GB, to make sure
>  we handle BAR sizes larger than 2 GB (for 64-bit BARs) correctly.
> -Running the consecutive BAR test in pci_endpoint_test.c to make sure that
>  the address translation works correctly.
> 
> 
> Texas Instruments kernel developers, if would be very nice if you could
> help out with testing on Keystone.
> 
> 
> Changes since V2:
> -When looping in dw_pcie_ep_init_non_sticky_registers(), use the index
>  that we read from PCI_REBAR_CTRL (e.g. a platform could have BARs 0-2
>  as programmable, and BARs 3-5 resizable, so we need to read the index).
> 
> 
> Kind regards,
> Niklas
> 
> Niklas Cassel (6):
>   PCI: endpoint: Add BAR type BAR_RESIZABLE
>   PCI: dwc: ep: Move dw_pcie_ep_find_ext_capability()
>   PCI: dwc: endpoint: Add support for BAR type BAR_RESIZABLE
>   PCI: keystone: Describe resizable BARs as resizable BARs
>   PCI: keystone: Specify correct alignment requirement
>   PCI: dw-rockchip: Describe resizable BARs as resizable BARs
> 
>  drivers/pci/controller/dwc/pci-keystone.c     |   6 +-
>  .../pci/controller/dwc/pcie-designware-ep.c   | 231 +++++++++++++++---
>  drivers/pci/controller/dwc/pcie-dw-rockchip.c |  22 +-
>  drivers/pci/endpoint/pci-epf-core.c           |   4 +
>  include/linux/pci-epc.h                       |   3 +
>  5 files changed, 219 insertions(+), 47 deletions(-)
> 
> -- 
> 2.47.1
> 

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Re: [PATCH v3 6/6] PCI: dw-rockchip: Describe resizable BARs as resizable BARs

[Manivannan Sadhasivam]

On Mon, Jan 13, 2025 at 11:27:37AM +0100, Niklas Cassel wrote:
> Looking at "11.4.4.29 USP_PCIE_RESBAR Registers Summary" in the rk3588 TRM,
> we can see that none of the BARs are Fixed BARs, but actually Resizable
> BARs.
> 
> I couldn't find any reference in the rk3568 TRM, but looking at the
> downstream PCIe endpoint driver, rk3568 and rk3588 are treated as the same,
> so the BARs on rk3568 must also be Resizable BARs.
> 
> Now when we actually have support for Resizable BARs, let's configure
> these BARs as such.
> 
> Signed-off-by: Niklas Cassel <cassel@kernel.org>

Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>

- Mani

> ---
>  drivers/pci/controller/dwc/pcie-dw-rockchip.c | 22 +++++++++----------
>  1 file changed, 11 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
> index ce4b511bff9b..6a307a961756 100644
> --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c
> +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
> @@ -273,12 +273,12 @@ static const struct pci_epc_features rockchip_pcie_epc_features_rk3568 = {
>  	.msi_capable = true,
>  	.msix_capable = true,
>  	.align = SZ_64K,
> -	.bar[BAR_0] = { .type = BAR_FIXED, .fixed_size = SZ_1M, },
> -	.bar[BAR_1] = { .type = BAR_FIXED, .fixed_size = SZ_1M, },
> -	.bar[BAR_2] = { .type = BAR_FIXED, .fixed_size = SZ_1M, },
> -	.bar[BAR_3] = { .type = BAR_FIXED, .fixed_size = SZ_1M, },
> -	.bar[BAR_4] = { .type = BAR_FIXED, .fixed_size = SZ_1M, },
> -	.bar[BAR_5] = { .type = BAR_FIXED, .fixed_size = SZ_1M, },
> +	.bar[BAR_0] = { .type = BAR_RESIZABLE, },
> +	.bar[BAR_1] = { .type = BAR_RESIZABLE, },
> +	.bar[BAR_2] = { .type = BAR_RESIZABLE, },
> +	.bar[BAR_3] = { .type = BAR_RESIZABLE, },
> +	.bar[BAR_4] = { .type = BAR_RESIZABLE, },
> +	.bar[BAR_5] = { .type = BAR_RESIZABLE, },
>  };
>  
>  /*
> @@ -293,12 +293,12 @@ static const struct pci_epc_features rockchip_pcie_epc_features_rk3588 = {
>  	.msi_capable = true,
>  	.msix_capable = true,
>  	.align = SZ_64K,
> -	.bar[BAR_0] = { .type = BAR_FIXED, .fixed_size = SZ_1M, },
> -	.bar[BAR_1] = { .type = BAR_FIXED, .fixed_size = SZ_1M, },
> -	.bar[BAR_2] = { .type = BAR_FIXED, .fixed_size = SZ_1M, },
> -	.bar[BAR_3] = { .type = BAR_FIXED, .fixed_size = SZ_1M, },
> +	.bar[BAR_0] = { .type = BAR_RESIZABLE, },
> +	.bar[BAR_1] = { .type = BAR_RESIZABLE, },
> +	.bar[BAR_2] = { .type = BAR_RESIZABLE, },
> +	.bar[BAR_3] = { .type = BAR_RESIZABLE, },
>  	.bar[BAR_4] = { .type = BAR_RESERVED, },
> -	.bar[BAR_5] = { .type = BAR_FIXED, .fixed_size = SZ_1M, },
> +	.bar[BAR_5] = { .type = BAR_RESIZABLE, },
>  };
>  
>  static const struct pci_epc_features *
> -- 
> 2.47.1
> 

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