From: Yao Zi <ziyao@disroot.org>
To: Heiko Stuebner <heiko@sntech.de>,
Andi Shyti <andi.shyti@kernel.org>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Jonas Karlman <jonas@kwiboo.se>, Yao Zi <ziyao@disroot.org>,
Chukun Pan <amadeus@jmu.edu.cn>
Cc: linux-arm-kernel@lists.infradead.org,
linux-rockchip@lists.infradead.org, linux-i2c@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: [PATCH 2/3] arm64: dts: rockchip: Add I2C controllers for RK3528
Date: Sun, 9 Mar 2025 07:06:02 +0000 [thread overview]
Message-ID: <20250309070603.35254-3-ziyao@disroot.org> (raw)
In-Reply-To: <20250309070603.35254-1-ziyao@disroot.org>
Describe I2C controllers shipped by RK3528 in devicetree.
Signed-off-by: Yao Zi <ziyao@disroot.org>
---
arch/arm64/boot/dts/rockchip/rk3528.dtsi | 104 +++++++++++++++++++++++
1 file changed, 104 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3528.dtsi b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
index 04ca2e2b3e9b..860b6057e5c2 100644
--- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
@@ -19,6 +19,14 @@ / {
#size-cells = <2>;
aliases {
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c4 = &i2c4;
+ i2c5 = &i2c5;
+ i2c6 = &i2c6;
+ i2c7 = &i2c7;
gpio0 = &gpio0;
gpio1 = &gpio1;
gpio2 = &gpio2;
@@ -466,6 +474,102 @@ uart7: serial@ffa28000 {
status = "disabled";
};
+ i2c0: i2c@ffa50000 {
+ compatible = "rockchip,rk3528-i2c",
+ "rockchip,rk3399-i2c";
+ reg = <0x0 0xffa50000 0x0 0x1000>;
+ clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>;
+ clock-names = "i2c", "pclk";
+ interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@ffa58000 {
+ compatible = "rockchip,rk3528-i2c",
+ "rockchip,rk3399-i2c";
+ reg = <0x0 0xffa58000 0x0 0x1000>;
+ clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>;
+ clock-names = "i2c", "pclk";
+ interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@ffa60000 {
+ compatible = "rockchip,rk3528-i2c",
+ "rockchip,rk3399-i2c";
+ reg = <0x0 0xffa60000 0x0 0x1000>;
+ clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>;
+ clock-names = "i2c", "pclk";
+ interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@ffa68000 {
+ compatible = "rockchip,rk3528-i2c",
+ "rockchip,rk3399-i2c";
+ reg = <0x0 0xffa68000 0x0 0x1000>;
+ clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>;
+ clock-names = "i2c", "pclk";
+ interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c4: i2c@ffa70000 {
+ compatible = "rockchip,rk3528-i2c",
+ "rockchip,rk3399-i2c";
+ reg = <0x0 0xffa70000 0x0 0x1000>;
+ clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>;
+ clock-names = "i2c", "pclk";
+ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c5: i2c@ffa78000 {
+ compatible = "rockchip,rk3528-i2c",
+ "rockchip,rk3399-i2c";
+ reg = <0x0 0xffa78000 0x0 0x1000>;
+ clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>;
+ clock-names = "i2c", "pclk";
+ interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c6: i2c@ffa80000 {
+ compatible = "rockchip,rk3528-i2c",
+ "rockchip,rk3399-i2c";
+ reg = <0x0 0xffa80000 0x0 0x1000>;
+ clocks = <&cru CLK_I2C6>, <&cru PCLK_I2C6>;
+ clock-names = "i2c", "pclk";
+ interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c7: i2c@ffa88000 {
+ compatible = "rockchip,rk3528-i2c",
+ "rockchip,rk3399-i2c";
+ reg = <0x0 0xffa88000 0x0 0x1000>;
+ clocks = <&cru CLK_I2C7>, <&cru PCLK_I2C7>;
+ clock-names = "i2c", "pclk";
+ interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
saradc: adc@ffae0000 {
compatible = "rockchip,rk3528-saradc";
reg = <0x0 0xffae0000 0x0 0x10000>;
--
2.48.1
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next prev parent reply other threads:[~2025-03-09 7:13 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-03-09 7:06 [PATCH 0/3] Support I2C controllers in RK3528 Yao Zi
2025-03-09 7:06 ` [PATCH 1/3] dt-bindings: i2c: i2c-rk3x: Add compatible string for RK3528 Yao Zi
2025-03-09 19:47 ` Heiko Stübner
2025-03-10 16:38 ` Conor Dooley
2025-03-11 22:08 ` Andi Shyti
2025-03-09 7:06 ` Yao Zi [this message]
2025-03-09 8:00 ` [PATCH 2/3] arm64: dts: rockchip: Add I2C controllers " Chukun Pan
2025-03-10 7:22 ` Yao Zi
2025-03-09 18:23 ` Jonas Karlman
2025-03-09 7:06 ` [PATCH 3/3] arm64: dts: rockchip: Add onboard EEPROM for Radxa E20C Yao Zi
2025-03-10 7:00 ` Chukun Pan
2025-03-10 7:15 ` Yao Zi
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