Re: [PATCH] iio: adc: rockchip: Fix clock initialization sequence

From: Jonathan Cameron <jic23@kernel.org>
To: Heiko Stuebner <heiko@sntech.de>
Cc: Simon Xue <xxm@rock-chips.com>,
	Lars-Peter Clausen <lars@metafoo.de>,
	Andy Shevchenko <andy.shevchenko@gmail.com>,
	Shreeya Patel <shreeya.patel@collabora.com>,
	linux-iio@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH] iio: adc: rockchip: Fix clock initialization sequence
Date: Sat, 15 Mar 2025 18:40:28 +0000	[thread overview]
Message-ID: <20250315184028.46053659@jic23-huawei> (raw)
In-Reply-To: <10623626.nUPlyArG6x@phil>

On Wed, 12 Mar 2025 08:00:54 +0100
Heiko Stuebner <heiko@sntech.de> wrote:

> Am Mittwoch, 12. März 2025, 07:20:16 MEZ schrieb Simon Xue:
> > clock_set_rate should be executed after devm_clk_get_enabled.
> > 
> > Fixes: 97ad10bb2901 ("iio: adc: rockchip_saradc: Make use of devm_clk_get_enabled")
> > Signed-off-by: Simon Xue <xxm@rock-chips.com>  
> 
> Reviewed-by: Heiko Stuebner <heiko@sntech.de>
ouch.

Applied and marked for stable.

Thanks,

Jonathan

> 
> > ---
> >  drivers/iio/adc/rockchip_saradc.c | 17 ++++++++---------
> >  1 file changed, 8 insertions(+), 9 deletions(-)
> > 
> > diff --git a/drivers/iio/adc/rockchip_saradc.c b/drivers/iio/adc/rockchip_saradc.c
> > index a29e54754c8f..ab4de67fb135 100644
> > --- a/drivers/iio/adc/rockchip_saradc.c
> > +++ b/drivers/iio/adc/rockchip_saradc.c
> > @@ -480,15 +480,6 @@ static int rockchip_saradc_probe(struct platform_device *pdev)
> >  	if (info->reset)
> >  		rockchip_saradc_reset_controller(info->reset);
> >  
> > -	/*
> > -	 * Use a default value for the converter clock.
> > -	 * This may become user-configurable in the future.
> > -	 */
> > -	ret = clk_set_rate(info->clk, info->data->clk_rate);
> > -	if (ret < 0)
> > -		return dev_err_probe(&pdev->dev, ret,
> > -				     "failed to set adc clk rate\n");
> > -
> >  	ret = regulator_enable(info->vref);
> >  	if (ret < 0)
> >  		return dev_err_probe(&pdev->dev, ret,
> > @@ -515,6 +506,14 @@ static int rockchip_saradc_probe(struct platform_device *pdev)
> >  	if (IS_ERR(info->clk))
> >  		return dev_err_probe(&pdev->dev, PTR_ERR(info->clk),
> >  				     "failed to get adc clock\n");
> > +	/*
> > +	 * Use a default value for the converter clock.
> > +	 * This may become user-configurable in the future.
> > +	 */
> > +	ret = clk_set_rate(info->clk, info->data->clk_rate);
> > +	if (ret < 0)
> > +		return dev_err_probe(&pdev->dev, ret,
> > +				     "failed to set adc clk rate\n");
> >  
> >  	platform_set_drvdata(pdev, indio_dev);
> >  
> >   
> 
> 
> 
> 

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