From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EB834C369B2 for ; Thu, 17 Apr 2025 15:29:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=E6CGlW9hQf2Ge/Id91DWzKWy11xdCn1ytvqvBo5sXvg=; b=YdWGxQfKAtCr4G cu1Pky1H4SY84rONRSUc9WTVaqGAvx0/W31nxeVRXa8U3QPOjt8CVHUgNqvJGydZZNJfw3aBfsFWZ 3e2YrOcLsTIoguJZSA8tcw7jle6qS8G8AzpljJNegsvnYYzCCnYdB7msvpU2gTeytLfc1Bs/WZIjH 9Lkv/Lf5xWZer3BC1ukvBtEG3gzmLbaLMcpMvdUimGw+htasi3Wnv4N7BQTOKdSsjPU2eWuxKXI9j G1bIhe05b1SpFOrC2J58igALPuphPpAqB/I+FLgAyfslyz3ks4K1r8tMwA+JKg9jf/25utlVIoNXa EaX5MppIkCafmLetlbNg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1u5RAj-0000000DW4T-3OhC; Thu, 17 Apr 2025 15:29:01 +0000 Received: from layka.disroot.org ([178.21.23.139]) by bombadil.infradead.org with esmtps (Exim 4.98.2 #2 (Red Hat Linux)) id 1u5QMv-0000000DLXe-3NoO; Thu, 17 Apr 2025 14:37:35 +0000 Received: from mail01.disroot.lan (localhost [127.0.0.1]) by disroot.org (Postfix) with ESMTP id 88CB125C5C; Thu, 17 Apr 2025 16:37:32 +0200 (CEST) X-Virus-Scanned: SPAM Filter at disroot.org Received: from layka.disroot.org ([127.0.0.1]) by localhost (disroot.org [127.0.0.1]) (amavis, port 10024) with ESMTP id aHuPYRFQIArQ; Thu, 17 Apr 2025 16:37:31 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=disroot.org; s=mail; t=1744900651; bh=5KKTJC0BGgZzdJ44qMWE7iL95oyAAWhSmtBAKPP/Ro4=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=KgffntZlzNEDdRqy70ufQIlVyxM+n/R3CMYZA2XOTU6SnDNcryQp5MoPm7k/FsTXb 4hJ/N5pXZllUfDqscZ+oU7XarxvoXFCIYe11fTb0nbS6JAZjDlSfUz0lXuQWovID+Z +bc+fjUMrAuCKUn5PulWzMm3tVWMuE0cyMj3qI7XxMkHn9NEgtg30zjDyKNaFpAD83 OClxwtKdWvgIcv/lt/YTArikEmBpHz2MUfAZtoOd/7lloFIzCDuU9+jxQipV2LtjJc 0xEq64Wm5fng2RSsyv0HuztHaOaDSzi56YwfgK4zwB4qNxJc/xESLF7J7Dx9663cuE ACpSXXM30mTPg== From: Yao Zi To: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Michael Turquette , Stephen Boyd , Shresth Prasad , Cristian Ciocaltea , Detlev Casanova , Jonas Karlman , Chukun Pan Cc: linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Yao Zi Subject: [PATCH v4 4/5] arm64: dts: rockchip: Add SDMMC/SDIO controllers for RK3528 Date: Thu, 17 Apr 2025 14:36:46 +0000 Message-ID: <20250417143647.43860-5-ziyao@disroot.org> In-Reply-To: <20250417143647.43860-1-ziyao@disroot.org> References: <20250417143647.43860-1-ziyao@disroot.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250417_073733_988093_58BF9856 X-CRM114-Status: UNSURE ( 7.15 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org RK3528 features two SDIO controllers and one SD/MMC controller, describe them in devicetree. Since their sample and drive clocks are located in the VO and VPU GRFs, corresponding syscons are added to make these clocks available. Signed-off-by: Yao Zi --- arch/arm64/boot/dts/rockchip/rk3528.dtsi | 69 ++++++++++++++++++++++++ 1 file changed, 69 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3528.dtsi b/arch/arm64/boot/dts/rockchip/rk3528.dtsi index 826f9be0be19..931d4ac004c5 100644 --- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi @@ -321,6 +321,16 @@ qos_vpu: qos@ff280400 { reg = <0x0 0xff280400 0x0 0x20>; }; + vpu_grf: syscon@ff340000 { + compatible = "rockchip,rk3528-vpu-grf", "syscon"; + reg = <0x0 0xff340000 0x0 0x8000>; + }; + + vo_grf: syscon@ff360000 { + compatible = "rockchip,rk3528-vo-grf", "syscon"; + reg = <0x0 0xff360000 0x0 0x10000>; + }; + cru: clock-controller@ff4a0000 { compatible = "rockchip,rk3528-cru"; reg = <0x0 0xff4a0000 0x0 0x30000>; @@ -501,6 +511,65 @@ sdhci: mmc@ffbf0000 { status = "disabled"; }; + sdio0: mmc@ffc10000 { + compatible = "rockchip,rk3528-dw-mshc", + "rockchip,rk3288-dw-mshc"; + reg = <0x0 0xffc10000 0x0 0x4000>; + clocks = <&cru HCLK_SDIO0>, + <&cru CCLK_SRC_SDIO0>, + <&cru SCLK_SDIO0_DRV>, + <&cru SCLK_SDIO0_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + interrupts = ; + max-frequency = <200000000>; + pinctrl-names = "default"; + pinctrl-0 = <&sdio0_bus4>, <&sdio0_clk>, <&sdio0_cmd>; + resets = <&cru SRST_H_SDIO0>; + reset-names = "reset"; + status = "disabled"; + }; + + sdio1: mmc@ffc20000 { + compatible = "rockchip,rk3528-dw-mshc", + "rockchip,rk3288-dw-mshc"; + reg = <0x0 0xffc20000 0x0 0x4000>; + clocks = <&cru HCLK_SDIO1>, + <&cru CCLK_SRC_SDIO1>, + <&cru SCLK_SDIO1_DRV>, + <&cru SCLK_SDIO1_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + interrupts = ; + max-frequency = <200000000>; + pinctrl-names = "default"; + pinctrl-0 = <&sdio1_bus4>, <&sdio1_clk>, <&sdio1_cmd>; + resets = <&cru SRST_H_SDIO1>; + reset-names = "reset"; + status = "disabled"; + }; + + sdmmc: mmc@ffc30000 { + compatible = "rockchip,rk3528-dw-mshc", + "rockchip,rk3288-dw-mshc"; + reg = <0x0 0xffc30000 0x0 0x4000>; + clocks = <&cru HCLK_SDMMC0>, + <&cru CCLK_SRC_SDMMC0>, + <&cru SCLK_SDMMC_DRV>, + <&cru SCLK_SDMMC_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + interrupts = ; + max-frequency = <150000000>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_bus4>, <&sdmmc_clk>, <&sdmmc_cmd>, + <&sdmmc_det>; + resets = <&cru SRST_H_SDMMC0>; + reset-names = "reset"; + rockchip,default-sample-phase = <90>; + status = "disabled"; + }; + dmac: dma-controller@ffd60000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x0 0xffd60000 0x0 0x4000>; -- 2.49.0 _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip