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From: Krzysztof Kozlowski <krzk@kernel.org>
To: Tomeu Vizoso <tomeu@tomeuvizoso.net>
Cc: "Heiko Stuebner" <heiko@sntech.de>,
	linux-doc@vger.kernel.org, dri-devel@lists.freedesktop.org,
	"David Airlie" <airlied@gmail.com>,
	"Sumit Semwal" <sumit.semwal@linaro.org>,
	"Simona Vetter" <simona@ffwll.ch>,
	"Rob Herring" <robh@kernel.org>,
	"Jonathan Corbet" <corbet@lwn.net>,
	"Sebastian Reichel" <sebastian.reichel@collabora.com>,
	linux-rockchip@lists.infradead.org, linux-media@vger.kernel.org,
	devicetree@vger.kernel.org, "Conor Dooley" <conor+dt@kernel.org>,
	"Jeff Hugo" <jeff.hugo@oss.qualcomm.com>,
	"Maarten Lankhorst" <maarten.lankhorst@linux.intel.com>,
	"Maxime Ripard" <mripard@kernel.org>,
	linaro-mm-sig@lists.linaro.org,
	linux-arm-kernel@lists.infradead.org,
	"Oded Gabbay" <ogabbay@kernel.org>,
	linux-kernel@vger.kernel.org,
	"Thomas Zimmermann" <tzimmermann@suse.de>,
	"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
	"Christian König" <christian.koenig@amd.com>
Subject: Re: [PATCH v4 01/10] dt-bindings: npu: rockchip,rknn: Add bindings
Date: Tue, 20 May 2025 09:33:54 +0200	[thread overview]
Message-ID: <20250520-hypnotic-pink-lori-dece51@kuoka> (raw)
In-Reply-To: <20250519-6-10-rocket-v4-1-d6dff6b4c0ae@tomeuvizoso.net>

On Mon, May 19, 2025 at 03:43:33PM GMT, Tomeu Vizoso wrote:
> Add the bindings for the Neural Processing Unit IP from Rockchip.
> 
> v2:
> - Adapt to new node structure (one node per core, each with its own
>   IOMMU)
> - Several misc. fixes from Sebastian Reichel
> 
> v3:
> - Split register block in its constituent subblocks, and only require
>   the ones that the kernel would ever use (Nicolas Frattaroli)
> - Group supplies (Rob Herring)
> - Explain the way in which the top core is special (Rob Herring)
> 
> v4:
> - Change required node name to npu@ (Rob Herring and Krzysztof Kozlowski)
> - Remove unneeded items: (Krzysztof Kozlowski)
> - Fix use of minItems/maxItems (Krzysztof Kozlowski)
> - Add reg-names to list of required properties (Krzysztof Kozlowski)
> - Fix example (Krzysztof Kozlowski)
> 
> Signed-off-by: Tomeu Vizoso <tomeu@tomeuvizoso.net>
> Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>

This order of SoB is still odd. You as person sending it should be the
last signing person. Are you sure you are using b4 for managing
trailers? I would expect it to re-order these on every update and this
is already v4.

> ---
>  .../bindings/npu/rockchip,rknn-core.yaml           | 149 +++++++++++++++++++++

Filename matching compatible, so rockchip,rk3588-rknn-core.yaml

>  1 file changed, 149 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/npu/rockchip,rknn-core.yaml b/Documentation/devicetree/bindings/npu/rockchip,rknn-core.yaml
> new file mode 100644
> index 0000000000000000000000000000000000000000..fafd0b01da215c7396262012988e364ef07ea137
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/npu/rockchip,rknn-core.yaml
> @@ -0,0 +1,149 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/npu/rockchip,rknn-core.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Neural Processing Unit IP from Rockchip
> +
> +maintainers:
> +  - Tomeu Vizoso <tomeu@tomeuvizoso.net>
> +
> +description:
> +  Rockchip IP for accelerating inference of neural networks, based on NVIDIA's
> +  open source NVDLA IP.
> +
> +  There is to be a node per each core in the NPU. In Rockchip's design there
> +  will be one core that is special and needs to be powered on before any of the
> +  other cores can be used. This special core is called the top core and should
> +  have the compatible string that corresponds to top cores.
> +
> +properties:
> +  $nodename:
> +    pattern: '^npu@[a-f0-9]+$'
> +
> +  compatible:
> +    oneOf:

Drop... if you followed my advice you would notice it is not necessary.

> +      - enum:
> +          - rockchip,rk3588-rknn-core-top
> +      - enum:
> +          - rockchip,rk3588-rknn-core

My comments were only partially implemented. This syntax is really not
readable and not necessary and I asked to make it part of previous enum.
This is just one enum:

compatible:
  enum:
    - foo
    - bar

Best regards,
Krzysztof


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  reply	other threads:[~2025-05-20  7:36 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-05-19 13:43 [PATCH v4 00/10] New DRM accel driver for Rockchip's RKNN NPU Tomeu Vizoso
2025-05-19 13:43 ` [PATCH v4 01/10] dt-bindings: npu: rockchip,rknn: Add bindings Tomeu Vizoso
2025-05-20  7:33   ` Krzysztof Kozlowski [this message]
2025-05-19 13:43 ` [PATCH v4 02/10] arm64: dts: rockchip: Add nodes for NPU and its MMU to rk3588s Tomeu Vizoso
2025-05-19 13:43 ` [PATCH v4 03/10] arm64: dts: rockchip: Enable the NPU on quartzpro64 Tomeu Vizoso
2025-05-19 13:43 ` [PATCH v4 04/10] accel/rocket: Add registers header Tomeu Vizoso
2025-05-19 13:43 ` [PATCH v4 05/10] accel/rocket: Add a new driver for Rockchip's NPU Tomeu Vizoso
2025-05-20  7:37   ` Krzysztof Kozlowski
2025-05-19 13:43 ` [PATCH v4 06/10] accel/rocket: Add IOCTL for BO creation Tomeu Vizoso
2025-05-30 19:23   ` Markus Elfring
2025-05-19 13:43 ` [PATCH v4 07/10] accel/rocket: Add job submission IOCTL Tomeu Vizoso
2025-05-19 13:43 ` [PATCH v4 08/10] accel/rocket: Add IOCTLs for synchronizing memory accesses Tomeu Vizoso
2025-05-19 13:43 ` [PATCH v4 09/10] arm64: dts: rockchip: add pd_npu label for RK3588 power domains Tomeu Vizoso
2025-05-19 13:43 ` [PATCH v4 10/10] arm64: dts: rockchip: enable NPU on ROCK 5B Tomeu Vizoso
2025-05-30 18:50 ` [PATCH v4 00/10] New DRM accel driver for Rockchip's RKNN NPU Jagan Teki
2025-06-01  6:41   ` Tomeu Vizoso

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